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US 11,777,011 B2Granted
Integrated circuitry, method used in the fabrication of a vertical transistor, and method used in the fabrication of integrated circuitry
AssigneeMicron Technology, Inc.
InventorsMasihhur R. Laskar, Jeffery B. Hull, Hung-Wei Liu
Life of this patent
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Abstract
Integrated circuitry comprises an electronic component. Insulative silicon dioxide is adjacent the electronic component. The insulative silicon dioxide has at least one of (a) and (b), where: (a): an average concentration of elemental-form H of 0.002 to 0.5 atomic percent; and (b): an average concentration of elemental-form N of 0.005 to 0.3 atomic percent. Other embodiments, including method, are disclosed.
Claims20
A method used in the fabrication of a vertical transistor, comprising:
- forming a bottom material, a top material, and a middle material vertically between the bottom and top materials;
- the bottom, top, and middle materials respectively comprising a bottom source/drain region, a top source/drain region, and a channel region vertically between the bottom and top source/drain regions in a finished construction of the vertical transistor, the bottom material having a substantially planar top;
- flowing a liquid comprising spin-on-dielectric to be laterally-aside the bottom material;
- microwave annealing the spin-on-dielectric to form insulative silicon dioxide having a substantially planar top that is adjacent the substantially planar top of the bottom material, the insulative silicon dioxide having at least one of (a) and (b), where:
- (a):
- an average concentration of elemental-form H of 0.002 to 0.5 atomic percent;
- and
- (b):
- an average concentration of elemental-form N of 0.005 to 0.3 atomic percent;
- forming conductive material against the substantially planar top of the insulative silicon dioxide to form a gate operatively aside the middle material;
- and
- the substantially planar top of the insulative silicon dioxide and the substantially planar top of the bottom material are each horizontal, the substantially planar top of the insulative silicon dioxide and the substantially planar top of the bottom material being coplanar relative to each other.
9 more elements
A method used in the fabrication of a vertical transistor, comprising:
- forming a bottom material, a top material, and a middle material vertically between the bottom and top materials;
- the bottom, top, and middle materials respectively comprising a bottom source/drain region, a top source/drain region, and a channel region vertically between the bottom and top source/drain regions in a finished construction of the vertical transistor, the bottom material having a substantially planar top;
- flowing a liquid comprising spin-on-dielectric to be laterally-aside the bottom material;
- microwave annealing the spin-on-dielectric to form insulative silicon dioxide having a substantially planar top that is adjacent the substantially planar top of the bottom material, the insulative silicon dioxide having at least one of (a) and (b), where:
- (a):
- an average concentration of elemental-form H of 0.002 to 0.5 atomic percent;
- and
- (b):
- an average concentration of elemental-form N of 0.005 to 0.3 atomic percent;
- forming conductive material against the substantially planar top of the insulative silicon dioxide to form a gate operatively aside the middle material;
- and
- the substantially planar bottom surface of the gate and the substantially planar bottom surface of the middle material are each horizontal, the substantially planar bottom surface of the gate and the substantially planar bottom surface of the middle material being coplanar relative to each other.
9 more elements
Dependencies are inferred from the claim text.