Method for fabricating memory device

A method for fabricating memory device, comprising:

• forming a cell structure on a substrate, wherein the cell structure comprises a first gate structure and a second gate structure disposed on a substrate and an insulating layer in contact between the first gate structure and the second gate structure, wherein the first gate structure and the second gate structure are planarized and the first gate structure is for storing charges;
• patterning the first gate structure and the second gate structure to have a shallow indent above the insulating layer;
• and
• forming an isolation structure in the shallow indent to have a shallow indent isolation, wherein forming the cell structure comprises:
• forming an oxide layer on the substrate;
• forming a first-stage first gate structure, having a charge storage layer with a portion of the oxide layer on the substrate, a first polysilicon layer on the charge storage layer, a dielectric layer on the first polysilicon layer, a second polysilicon layer on the dielectric layer, and a sidewall insulating layer on a sidewall of the first polysilicon layer, the dielectric layer and the second polysilicon layer;
• forming a third polysilicon layer over the first-stage first gate structure and the oxide layer on the substrate;
• polishing the third polysilicon layer, the sidewall insulating layer and the second polysilicon layer until the dielectric layer is exposed;
• patterning the second polysilicon layer and the third polysilicon layer to have the first gate structure and the second gate structure, abutting to each other but isolated by the sidewall insulating layer;
• patterning the first gate structure, the sidewall insulating layer, and the second gate structure to have a shallow indent above the sidewall insulating layer, wherein the sidewall insulating layer becomes the insulating layer in contact between the first gate structure and the second gate structure;
• and
• forming the shallow indent isolation in the shallow indent.