SiC MOSFET with reduced channel length and high Vth
AssigneeAlpha and Omega Semiconductor International LP
InventorsDavid Sheridan, Arash Salemi, Madhur Bobde
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Abstract
A silicon carbide MOSFET device and method for making thereof are disclosed. The silicon carbide MOSFET device comprises a substrate heavily doped with a first conductivity type and an epitaxial layer lightly doped with the first conductivity type. A body region of a second conductivity type opposite the first is formed in epitaxial layer and an accumulation mode region of the first conductivity type is formed in the body region and an inversion mode region of the second conductivity type formed in the body region. The accumulation mode region is located between the inversion mode region and a junction field effect transistor (JFET) region of the epitaxial layer.
Claims15
A silicon carbide MOSFET comprising:
- a substrate heavily doped with a first conductivity type;
- an epitaxial layer lightly doped with the first conductivity type having a junction field effect transistor (JFET) region of the first conductivity type;
- a body region doped with a second conductivity type formed in the epitaxial layer wherein the second conductivity type is opposite the first conductivity type;
- an accumulation mode region doped with the first conductivity type formed in the body region and an inversion mode region of the second conductivity type formed in the body region, wherein the accumulation mode region is located between the JFET region and the inversion mode region;
- and
- a source region with the first conductivity type doped from a surface of the epitaxial layer to a depth deeper than a bottom of the inversion mode region.
A method for making a silicon carbide MOSFET comprising:
- a) forming an epitaxial layer lightly doped a first conductivity type on a substrate heavily doped with the first conductivity type;
- b) forming a junction field effect transistor (JFET) region and a body region in the epitaxial layer, wherein the JFET region is of the first conductivity type, and wherein the body region is of a second conductivity type, wherein the second conductivity type is opposite the first conductivity type;
- c) forming an accumulation mode implant region doped with the first conductivity type in the body region;
- d) forming an inversion mode region of the second conductivity type in the accumulation mode implant region precursor over the body region, wherein the accumulation mode region is located between the JFET region and the inversion mode region;
- and
- e) forming a source region with the first conductivity type doped from surface of the epitaxial layer to a depth deeper than a bottom of the inversion mode region.
Dependencies are inferred from the claim text.