Method of manufacturing integrated circuit device
AssigneeSamsung Electronics Co., Ltd.
InventorsHong-sik Shin, Heung-sik Park, Do-haing Lee, In-keun Lee, Seung-ho Chae, Ha-young Choi
Life of this patent
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Abstract
An integrated circuit device is provided. The integrated circuit device includes a fin-type active region that extends in a first direction on a substrate, a gate structure that intersects with the fin-type active region and extends in a second direction, perpendicular to the first direction, on the substrate, and a first contact structure that is disposed on the gate structure, and has a greater width at a top surface than a bottom surface thereof.
Claims18
A method of manufacturing an integrated circuit device, comprising:
- forming a gate structure on a fin-type active region extending in a first direction on a substrate;
- forming an interlayer insulating layer to cover the gate structure;
- forming a contact hole in the interlayer insulating layer to expose a top surface of the gate structure, the contact hole including a step and having a top width greater than a bottom width;
- forming a liner layer on a side wall of the contact hole;
- forming an upper insulating liner and a lower insulating liner by removing a portion of the liner layer using a side wall rounding process;
- and
- forming a first contact in the contact hole, the first contact being connected to the gate structure,
- wherein during the forming of the upper insulating liner and the lower insulating liner, a portion of the interlayer insulating layer between the upper insulating liner and the lower insulating liner has a sloped side wall profile and is exposed to the contact hole.
A method of manufacturing an integrated circuit device, comprising:
- forming a gate structure on a fin-type active region extending in a first direction on a substrate;
- forming an interlayer insulating layer to cover the gate structure;
- forming a buried insulating layer having a buried insulating layer opening on the interlayer insulating layer;
- forming a contact hole by removing a first portion of the interlayer insulating layer in a position overlapping the buried insulating layer opening using the buried insulating layer as an etching mask;
- enlarging the buried insulating layer opening by performing a pull-back process to the buried insulating layer;
- enlarging an upper portion of the contact hole by removing a second portion of the interlayer insulating layer in a position overlapping the enlarged buried insulating layer opening such that a width of the upper portion of the contact hole is greater than a width of a lower portion of the contact hole;
- forming an upper insulating liner and a lower insulating liner on a side wall of the contact hole;
- and
- forming a first contact in the contact hole.
A method of manufacturing an integrated circuit device, comprising:
- forming a fin-type active region extending in a first direction on a substrate;
- forming a gate structure extending in a second direction on the fin-type active region;
- forming source/drain regions on both sides of the gate structure and on the fin-type active region;
- forming an interlayer insulating layer to cover the fin-type active region, the gate structure, and the source/drain regions;
- forming a first contact hole in the interlayer insulating layer to expose a top surface of the gate structure, the first contact hole including a step and having a top width greater than a bottom width;
- forming a second contact hole in the interlayer insulating layer to expose a top surface of the source/drain regions;
- forming a liner layer on a side wall of the first contact hole and a side wall of the second contact hole;
- forming an upper insulating liner and a lower insulating liner that form a continuous surface by removing a portion of the liner layer disposed on the side wall of the first contact hole using a side wall rounding process;
- and
- forming a first contact in the first contact hole and forming a second contact in the second contact hole, the first contact being connected to the gate structure, the second contact being connected to the source/drain regions,
- wherein after the side wall rounding process, the side wall of the first contact hole has a variably-sloped side wall profile.
Dependencies are inferred from the claim text.