Semiconductor device and manufacturing method thereof for selectively etching dummy fins

A method, comprising:

• forming a plurality of first fin structures and a plurality of second fin structures in a first region of a substrate and forming a plurality of third fin structures and a plurality of fourth fin structures in a second region of [[a]]the substrate different from the first region, wherein the third fin structures are spaced apart from the fourth fin structures;
• and
• forming a plurality of gate structures over the plurality of first fin structures, second fin structures, third fin structures, and fourth fin structures;
• etching the second fin structures and the fourth fin structures, wherein the second fin structures are etched more than the fourth fin structures;
• forming, after the etching, a plurality of first source/drain layers on the plurality of first fin structures and a plurality of second source/drain layers on the plurality of third fin structures, respectively, wherein at least some portions of the first source/drain layers protrude over the second fin structures.

A method, comprising:

• forming a plurality of first semiconductive structures and a plurality of first dielectric structures in a first region of a wafer and forming a plurality of second semiconductive structures and a plurality of second dielectric structures in a second region of the wafer different from the first region, wherein the first semiconductive structures, first dielectric structures, second semiconductive structures, and second dielectric structures each protrude vertically upwards, and wherein the second dielectric structures are spaced apart from the second semiconductive structures;
• forming a plurality of gate structures over the first semiconductive structures, first dielectric structures, second semiconductive structures, and second dielectric structures;
• reducing heights of the first dielectric structures more than the second dielectric structures;
• and
• epitaxially growing, after the reducing of the heights, a plurality of first source/drain layers on the plurality of first semiconductive structures and a plurality of second source/drain layers on the plurality of second semiconductive structures, respectively, wherein a lateral growth of the first source/drain layers is unaffected by the first dielectric structures, while a lateral growth of the second source/drain layers is stopped by the second dielectric structures.