Gate structures for stacked semiconductor devices

A semiconductor structure, comprising:

• a first transistor device, comprising:
• a first plurality of nanostructures;
• a first gate dielectric layer wrapping around each nanostructure of the first plurality of nanostructures;
• a first work function layer on the first gate dielectric layer;
• a first gate electrode on the first work function layer;
• and
• a first source/drain region in contact with the first plurality of nanostructures;
• a second transistor device, comprising:
• a second plurality of nanostructures;
• a second gate dielectric layer;
• a second work function layer on the second gate dielectric layer;
• a second gate electrode on the second work function layer;
• and
• a second source/drain region in contact with the second plurality of nanostructures;
• and
• a gate isolation structure between the first and second pluralities of nanostructures, wherein the gate isolation structure is in contact with a topmost nanostructure of the first plurality of nanostructures and a bottommost nanostructure of the second plurality of nanostructures.

A method, comprising:

• forming a first plurality of semiconductor layers on a substrate;
• forming a first isolation layer on the first plurality of semiconductor layers;
• forming a second plurality of semiconductor layers on the first isolation layer;
• removing portions of the first plurality of semiconductor layers to form a first plurality of nanostructures;
• forming a first gate structure on the first plurality of nanostructures;
• removing the first isolation layer;
• removing portions of the second plurality of semiconductor layers to form a second plurality of nanostructures;
• depositing a second isolation layer between the first and second pluralities of nanostructures;
• and
• forming a second gate structure on the second plurality of nanostructures.