Wrap-around trench contact structure and methods of fabrication

A method of fabricating an integrated circuit structure, the method comprising:

• forming a first semiconductor fin and a second semiconductor fin protruding from a semiconductor substrate;
• forming a trench isolation layer on the semiconductor substrate around a lower portion of the first semiconductor fin and around a lower portion of the second semiconductor fin, wherein an upper portion of the first semiconductor fin and an upper portion of the second semiconductor fin extend above the trench isolation layer;
• forming a gate structure over the upper portion of the first semiconductor fin and over the upper portion of the second semiconductor fin, the gate structure having a first side and a second side;
• forming a first epitaxial layer on the upper portion of the first semiconductor fin at the first side of the gate structure;
• forming a second epitaxial layer on the upper portion of the second semiconductor fin at the first side of the gate structure, the second epitaxial layer discontinuous from the first epitaxial layer, wherein there is no silicide between the first epitaxial layer and the second epitaxial layer;
• forming a contact metal over the first epitaxial layer and over the second epitaxial layer, the contact metal between the first and second epitaxial layers, the contact metal on a first portion of the trench isolation layer between the first epitaxial layer and the second epitaxial layer, and the contact metal having an uppermost surface, wherein the contact metal is not a silicide;
• and
• forming a dielectric spacer between the contact metal and the gate structure, the dielectric spacer having an uppermost surface at a same level as the uppermost surface of the contact metal.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a semiconductor substrate having a first semiconductor fin and a second semiconductor fin protruding therefrom;
• a trench isolation layer on the semiconductor substrate around a lower portion of the first semiconductor fin and around a lower portion of the second semiconductor fin, wherein an upper portion of the first semiconductor fin and an upper portion of the second semiconductor fin extend above the trench isolation layer;
• a gate structure over the upper portion of the first semiconductor fin and over the upper portion of the second semiconductor fin, the gate structure having a first side and a second side;
• a first epitaxial layer on the upper portion of the first semiconductor fin at the first side of the gate structure;
• a second epitaxial layer on the upper portion of the second semiconductor fin at the first side of the gate structure, the second epitaxial layer discontinuous from the first epitaxial layer, wherein there is no silicide between the first epitaxial layer and the second epitaxial layer;
• a contact metal over the first epitaxial layer and over the second epitaxial layer, the contact metal between the first and second epitaxial layers, the contact metal on a first portion of the trench isolation layer between the first epitaxial layer and the second epitaxial layer, and the contact metal having an uppermost surface, wherein the contact metal is not a silicide;
• and
• a dielectric spacer between the contact metal and the gate structure, the dielectric spacer having an uppermost surface at a same level as the uppermost surface of the contact metal.