Gate cut with integrated etch stop layer
AssigneeTessera, Inc.
InventorsMarc A. Bergendahl, Andrew M. Greene, Rajasekhar Venigalla
Life of this patent
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Abstract
A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.
Claims22
A method of forming a semiconductor structure, the method comprising:
- forming a gate structure on first and second active regions of the semiconductor structure;
- removing a portion of the gate structure to define a first gate structure on the first active region and a second gate structure on the second active region, wherein the first and second gate structures are in-line with one another and spaced apart by a gate cut trench;
- forming a first etch stop layer in the gate cut trench;
- forming a first dielectric material on the first etch stop layer in a lower portion of the gate cut trench;
- forming a second etch stop layer on an upper surface of the first dielectric material;
- and
- forming a second dielectric material on the second etch stop layer in an upper portion of the gate cut trench.
Dependencies are inferred from the claim text.