BiMOS semiconductor device

Abstract

Provided is an n-channel BiMOS semiconductor device having a trench gate structure, the n-channel BiMOS semiconductor device including: an n+ drain layer; a parallel pn layer including n− drift and p pillar layers joined alternately; a composite layer including a p base layer and an n+ source layer, the n+ drain layer, the parallel pn layer, and the composite layer being provided in order; a high-resistance layer provided between a portion of the p base layer above the p pillar layer and the n+ source layer; and a high-resistance layer provided between the p pillar layer and the p base layer, the p pillar layer having an impurity concentration lower than that of the n− drift layer.

Dependencies are inferred from the claim text.