Integrated circuit filler and method thereof

A semiconductor device, comprising:

• a first circuit pattern defining a logical function;
• a second circuit pattern contiguous with the first circuit pattern, wherein the second circuit pattern includes a repeated pattern array associated with a failure mode of the first circuit pattern;
• and
• a third circuit pattern contiguous with the second circuit pattern, wherein the third circuit pattern includes an irregular pattern.

A memory circuit, comprising:

• a plurality of logic cells disposed within a first portion of the memory circuit;
• and
• a plurality of filler cells disposed within a second portion of the memory circuit, wherein some of the plurality of filler cells include a repeated pattern array, and wherein others of the plurality of filler cells include an irregular pattern;
• wherein each of the filler cells having the repeated pattern array abut at least one logic cell of the plurality of logic cells.