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US 11,776,944 B2Granted
Discrete three-dimensional processor
AssigneesHangZhou HaiCun Information Technology Co., Ltd., Guobiao Zhang
InventorGuobiao Zhang
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Abstract
A discrete three-dimensional (3-D) processor comprises communicatively coupled first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises at least a non-memory circuit and at least an off-die peripheral-circuit component of the 3D-M arrays. The first die does not comprise said off-die peripheral-circuit component. The non-memory circuit on the second die is not part of a memory.
Claims32
A discrete three-dimensional (3-D) processor, comprising:
- a plurality of storage-processing units (SPU's), each of said SPU's comprising a non-memory circuit and at least a three-dimensional memory (3D-M) array;
- a first die on a first semiconductor substrate, wherein said 3D-M array comprises memory cells stacked above said first semiconductor substrate;
- a second die on a second semiconductor substrate, wherein at least a portion of said non-memory circuit and at least another portion of an off-die peripheral-circuit component of said 3D-M array are disposed on said second semiconductor substrate;
- wherein, said non-memory circuit is not a part of a memory;
- said first and second dice are communicatively coupled by a plurality of inter-die connections;
- said first and second semiconductor substrates are separate semiconductor substrates.
3 more elements
Dependencies are inferred from the claim text.