Methods of forming microelectronic devices, and related microelectronic devices and electronic systems

A method of forming a microelectronic device, comprising:

• forming a semiconductor wafer comprising a semiconductor material, trenches within the semiconductor material, control logic devices overlying the semiconductor material, routing structures overlying the control logic devices, and contact structures extending from the semiconductor material to some of the routing structures;
• attaching an additional wafer to the semiconductor wafer using oxide-oxide bonding to form an assembly;
• vertically inverting the assembly;
• removing portions of the semiconductor material to expose portions of the contact structures after vertically inverting the assembly;
• forming contact pad structures on the exposed portions of the contact structures;
• attaching an additional semiconductor wafer comprising an additional semiconductor material to the assembly using additional oxide-oxide bonding after forming the contact pad structures;
• forming access devices using portions of the additional semiconductor material;
• forming word lines and digit lines operatively associated with the access devices;
• forming additional contact structures penetrating the word lines and the digit lines and extending to some of the contact pad structures;
• forming further contact structures extending to some other of the contact pad structures;
• forming storage node devices over and coupled to the access devices;
• and
• forming additional routing structures over the storage node devices, at least some of the additional routing structures coupled to the further contact structures.

A microelectronic device, comprising:

• array regions individually comprising:
• memory cells comprising access devices and storage node devices;
• digit lines coupled to the access devices and extending in a first direction;
• word lines coupled to the access devices and extending in a second direction orthogonal to the first direction;
• and
• control logic devices vertically offset from and in electrical communication with the memory cells;
• digit line exit regions horizontally alternating with the array regions in the first direction and individually comprising:
• portions of the digit lines extending beyond the array regions adjacent thereto;
• contact pad structures underlying the portions of the digit lines;
• digit line contact structures extending through at least some of the portions of the digit lines to the contact pad structures;
• routing structures underlying the contact pad structures and in electrical communication with some of the control logic devices;
• and
• contact structures extending from the contact pad structures to the routing structures;
• and
• word line exit regions horizontally alternating with the array regions in the second direction and individually comprising:
• portions of the word lines extending beyond the array regions adjacent thereto;
• additional contact pad structures underlying the portions of the word lines;
• word line contact structures extending through at least some of the portions of the word lines to the additional contact pad structures;
• additional routing structures underlying the additional contact pad structures and in electrical communication with some other of the control logic devices;
• and
• additional contact structures extending from the additional contact pad structures to the additional routing structures.

An electronic system, comprising:

• an input device;
• an output device;
• a processor device operably connected to the input device and the output device;
• and
• a memory device operably connected to the processor device and comprising:
• memory array regions each comprising dynamic random access memory (DRAM) cells, digit lines coupled to the DRAM cells, word lines coupled to the DRAM cells, and control logic devices vertically offset from and in electrical communication with the DRAM cells;
• a digit line contact region between two of the memory array regions neighboring one another in a first direction, the digit line contact region comprising:
• end portions of some of the digit lines extending past horizontal areas of the two of the memory array regions;
• conductive pads vertically underlying the some of the digit lines;
• digit line contacts vertically extending through the end portions of the some of the digit lines to the conductive pads;
• conductive routing vertically underlying the conductive pads;
• and
• conductive contacts vertically extending from the conductive pads to the conductive routing;
• and
• a word line contact region between two other of the memory array regions neighboring one another in a second direction perpendicular to the first direction, the word line contact region comprising:
• end portions of some of the word lines extending past horizontal areas of the two other of the memory array regions;
• additional conductive pads vertically underlying the some of the word lines;
• word line contacts vertically extending completely through the end portions of the some of the word lines to the additional conductive pads;
• additional conductive routing vertically underlying the additional conductive pads;
• and
• additional conductive contacts vertically extending from the additional conductive pads to the additional conductive routing.