Semiconductor package having stiffening structure
AssigneeSamsung Electronics Co., Ltd.
InventorsEunkyoung Choi, Suchang Lee, Yunseok Choi
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Abstract
A semiconductor package having a stiffening structure is disclosed. The semiconductor package includes a substrate, an interposer on the substrate, and a first logic chip, a second logic chip, memory stacks and stiffening chips, all of which are on the interposer. The first logic chip and the second logic chip are adjacent to each other. Each memory stack is adjacent to a corresponding one of the first logic chip and the second logic chip. Each memory stack includes a plurality of stacked memory chips. Each stiffening chip is disposed between corresponding ones of the memory stacks, to be aligned and overlap with a boundary area between the first logic chip and the second logic chip.
Claims20
A semiconductor package comprising:
- a substrate;
- an interposer on the substrate;
- and
- a first logic chip and a second logic chip on the interposer, the first logic chip and the second logic chip are side-by-side so as to be adjacent to each other;
- memory stacks including a plurality of stacked memory chips, each memory stack is adjacent to a corresponding one of the first logic chip and the second logic chip, the memory stacks on the interposer;
- and
- dummy chips on the interposer, the dummy chips between corresponding ones of the memory stacks, the dummy chips aligned with and overlapping a boundary area between the first logic chip and the second logic chip, wherein each of the dummy chips have a greater width than the boundary area such that a respective one of the dummy chips overlaps with a portion of the first logic chip and a portion of the second logic chip in a row direction, and wherein a minimum distance between the first logic chip and the second logic chip is smaller than a minimum distance between the memory stacks.
A semiconductor package comprising:
- a substrate;
- an interposer on the substrate;
- first and second logic chips on the interposer such that the first and second logic chips are adjacent to each other, the first and second logic chips being electrically connected through a wiring inside the interposer;
- first memory stacks at opposite side surfaces of the first logic chip, and second memory stacks at opposite side surfaces of the second logic chip;
- and
- dummy chips between the first memory stacks and the second memory stacks,
- wherein a minimum distance between the first logic chip and the second logic chip is smaller than a minimum distance between the first memory stacks and the second memory stacks,
- wherein the dummy chips are adjacent to a boundary area between the first logic chip and the second logic chip and aligned with an extension line of the boundary area, and
- wherein the dummy chips have a greater width than the boundary area such that a respective one of the dummy chips overlaps with a portion of the first logic chip and a portion of the second logic chip in a row direction, and wherein a minimum distance between the first logic chip and the second logic chip is smaller than a minimum distance between the first memory stacks and a minimum distance between the second memory stacks.
A semiconductor package comprising:
- a substrate;
- an interposer on the substrate;
- a plurality of logic chips on the interposer, adjacent to one another within 100 mm, and the logic chips are electrically connected through the interposer;
- a plurality of memory stacks on the interposer, each of the memory stacks includes a plurality of stacked memory chips, and through vias extending vertically through the memory chips;
- and
- a plurality of dummy chips on the interposer, longer sides of the dummy chips are parallel to shorter sides of the memory stacks, shorter sides of the dummy chips have a length corresponding to ½ or less of a length of longer sides of the memory stacks, and each of the dummy chips has a greater width than a boundary area between corresponding ones of the logic chips such that a respective one of the plurality of dummy chips horizontally overlaps with portions of the corresponding logic chips;
- and
- a molding compound surrounding side surfaces of the interposer, side surfaces of the logic chips, side surfaces of the memory stacks and side surfaces of the dummy chips,
- wherein a minimum distance between the logic chips is smaller than a minimum distance between the memory stacks.
Dependencies are inferred from the claim text.