Semiconductor package

A semiconductor package comprising:

• a first semiconductor chip including a first wiring structure;
• a first passivation layer which includes a first alignment key and a first bonding pad provided on the first wiring structure to be spaced apart from each other in a first direction;
• a second passivation layer which is provided on the first passivation layer, and includes a second alignment key, and a second bonding pad directly joined to the first bonding pad;
• and
• a second semiconductor chip including a second wiring structure spaced apart from the first wiring structure in a second direction different from the first direction by the second passivation layer,
• wherein a surface on which the first alignment key and the first wiring structure are in contact forms a same plane as a surface on which the first bonding pad and the first wiring structure are in contact,
• wherein a surface on which the second alignment key and the second wiring structure are in contact forms a same plane as a surface on which the second bonding pad and the second wiring structure are in contact,
• wherein the first alignment key includes an alignment part, and an opening which penetrates the alignment part and exposes at least a part of the first wiring structure, and
• wherein the second alignment key overlaps the opening in the second direction and does not overlap the alignment part in the second direction.

A semiconductor package comprising:

• a substrate which includes a first face including a connection pad, and a second face opposite to the first face in a first direction;
• a first connection terminal electrically connected to the connection pad, on the first face of the substrate;
• a first semiconductor chip which includes a first wiring structure on the second face of the substrate, the first wiring structure including a first wiring region in which a first wiring pattern is provided and a first alignment region in which the first wiring pattern is not provided, and a first penetration electrode electrically connected to the first connection terminal and the first wiring pattern;
• a first passivation layer which includes a first bonding pad provided on the first wiring pattern of the first wiring structure and electrically connected to the first wiring pattern, and a first alignment key provided on the first alignment region of the first wiring structure;
• a second passivation layer which includes a second bonding pad directly joined to the first bonding pad, and a second alignment key which does not overlap the first alignment key in the first direction, the second passivation layer being directly joined to the first passivation layer;
• and
• a second semiconductor chip including a second wiring structure on the second passivation layer, the second wiring structure including a second wiring region in which a second wiring pattern electrically connected to the second bonding pad is provided, and a second alignment region in which the second wiring pattern is not provided,
• wherein the second alignment key is provided on the second alignment region.