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US 11,776,913 B2Granted
Semiconductor package and a package-on-package including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsHwanpil Park, Dongho Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor package including: a first wiring structure; a semiconductor chip disposed on the first wiring structure; a second wiring structure disposed on the semiconductor chip and including a cavity; and a filling member between the first wiring structure and the second wiring structure and in the cavity, wherein an uppermost end of the filling member and an uppermost end of the second wiring structure are located at the same level.
Claims20
A semiconductor package, comprising:
- a first wiring structure;
- a semiconductor chip disposed on the first wiring structure;
- a second wiring structure disposed on the semiconductor chip and comprising a cavity;
- and
- a filling member between the first wiring structure and the second wiring structure and in the cavity,
- wherein an uppermost end of the filling member and an uppermost end of the second wiring structure are located at the same level from a first side of the cavity to a second side of the cavity opposite the first side.
3 more elements
A semiconductor package, comprising:
- a support wiring structure comprising a plurality of first base insulating layers and a plurality of first wiring patterns;
- a semiconductor chip disposed on the support wiring structure and electrically connected to a first portion of the plurality of first wiring patterns;
- a cover wiring structure disposed on the semiconductor chip and comprising at least one second base insulating layer, a plurality of second wiring patterns, an upper solder resist layer and a lower solder resist layer covering an upper surface and a lower surface of the at least one second base insulating layer, a plurality of solder resist patches disposed between the lower solder resist layer and the semiconductor chip and having a first width, and a cavity overlapping the semiconductor chip in a vertical direction and having an area less than an area of the semiconductor chip;
- a filling member surrounding side surfaces of the plurality of solder resist patches and comprising a filling protrusion filling a space between the support wiring structure and the cover wiring structure and the cavity;
- and
- a plurality of connection structures penetrating the filling member and connecting a second portion of the plurality of first wiring patterns and the plurality of second wiring patterns,
- wherein an upper surface of the filling protrusion and an upper surface of the upper solder resist layer are coplanar.
4 more elements
A semiconductor package, comprising:
- a first wiring structure;
- a second wiring structure, wherein the second wiring structure includes an opening;
- a semiconductor chip disposed between the first and second wiring structures, wherein the opening overlaps the semiconductor chip;
- a filling portion disposed between the first and second wiring structures, inside the opening and between the semiconductor chip and the second wiring structure, wherein an upper surface of the filling portion and an upper surface of the second wiring structure are coplanar with each other across the opening;
- and
- a solder resist pattern disposed between the semiconductor chip and the second wiring structure.
3 more elements
Dependencies are inferred from the claim text.