Semiconductor device with contact structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorChung-Liang Cheng
Life of this patent
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Abstract
A semiconductor process system etches thin films on semiconductor wafers. The semiconductor process system includes a machine learning based analysis model. The analysis model dynamically selects process conditions for an etching process by receiving static process conditions and target thin-film data. The analysis model identifies dynamic process conditions data that, together with the static process conditions data, result in predicted remaining thin-film data that matches the target thin-film data. The process system then uses the static and dynamic process conditions data for the next etching process.
Claims20
An integrated circuit, comprising:
- a first dielectric layer;
- a transistor including a gate terminal including a gate metal having a top surface substantially coplanar with a top surface of the first dielectric layer;
- a second dielectric layer on the top surface of the first dielectric layer;
- a first trench in the second dielectric layer exposing the gate metal and defining a sidewall of the second dielectric layer;
- a layer of titanium having:
- a planar bottom surface in contact with the top surface of the gate metal;
- and
- a convex top surface;
- a first layer of titanium nitride in the trench and having a concave bottom surface in contact with the convex top surface of the layer of titanium;
- a second layer of titanium nitride in the trench and having a concave bottom surface in contact with a top surface of the first layer of titanium nitride, the second layer of titanium nitride being in contact with the sidewall of the second dielectric layer and having a vertical extent in the trench higher than a vertical extent of the first layer of titanium nitride in the trench;
- and
- a conductive plug positioned in the trench and having a concave bottom surface in contact with a top surface of the second layer of titanium nitride.
A method, comprising:
- forming a dielectric layer on a terminal of a transistor;
- exposing the terminal by forming a trench in the dielectric layer;
- selecting parameters for an atomic layer etching process of a first titanium nitride layer;
- forming the first titanium nitride layer in the trench on the terminal of the transistor by etching the first titanium nitride layer to a selected height within the trench with the atomic layer etching process including the selected parameters;
- forming a second titanium nitride layer in the trench above the first titanium nitride layer and on a sidewall of the trench;
- and
- forming a cobalt plug in the trench.
An integrated circuit, comprising:
- a first dielectric layer;
- a transistor including a source/drain terminal having a top surface substantially coplanar with a top surface of the first dielectric layer;
- a second dielectric layer on the first dielectric layer;
- a first trench in the second dielectric layer exposing the source/drain terminal and defining a sidewall of the second dielectric layer;
- a silicide layer in contact with the top surface of the source/drain terminal in the trench;
- a metal layer on the silicide in the trench and including:
- a substantially planar bottom surface in contact with a top surface of the silicide layer;
- and
- a convex top surface;
- a first barrier layer having a concave bottom surface in contact with the convex top surface of the metal layer in the trench;
- a second barrier layer having a convex bottom surface in contact with a top surface of the first barrier layer, the second barrier layer in contact with the sidewall of the second dielectric layer and having a vertical extent in the trench higher than a vertical extent of the first barrier layer in the trench;
- and
- a cobalt plug positioned in the trench and in contact with the second barrier layer.
Dependencies are inferred from the claim text.