Via array design for multi-layer redistribution circuit structure

A semiconductor package, comprising:

• at least one semiconductor die;
• a molding compound surrounding the at least one semiconductor die;
• and
• a redistribution layer disposed on a lower surface of the molding compound, wherein the at least one semiconductor die is electrically connected to an interconnect structure of the redistribution layer, wherein the interconnect structure comprises:
• an intermediate via land pad;
• a cluster of upper conductive vias abutting the intermediate via land pad and electrically coupling the intermediate via land pad to an upper via land pad;
• and
• an array of lower conductive vias electrically coupling the intermediate via land pad with a lower circuit pad, wherein the array of lower conductive vias is arranged within a horseshoe-shaped via array region extending along a perimeter of the intermediate via land pad, wherein the intermediate via land pad and the upper via land pad are not concentric with respect to a central axis when viewed from above.

An interconnect structure for a redistribution layer, comprising:

• an intermediate via land pad;
• a cluster of upper conductive vias abutting the intermediate via land pad and electrically coupling the intermediate via land pad to an upper via land pad;
• and
• an array of lower conductive vias electrically coupling the intermediate via land pad with a lower circuit pad, wherein the cluster of upper conductive vias is disposed within a projected area of the upper via land pad on the intermediate via land pad, wherein the array of lower conductive vias is arranged on a rest portion of the intermediate via land pad outside the projected area and does not overlap with the cluster of upper conductive vias, wherein the intermediate via land pad and the upper via land pad are not concentric with respect to a central axis when viewed from above.