Sidewall interconnect metallization structures for integrated circuit devices

An integrated circuit (IC) interconnect structure, comprising:

• a first metallization level comprising a first conductive feature and a second conductive feature, wherein the first conductive feature is laterally adjacent to the second conductive feature with a space therebetween;
• a first dielectric material within the space and in contact with a first sidewall portion of at least the first conductive feature;
• a second dielectric material between the first metallization level and a second metallization level, wherein the second dielectric material extends into the space between the first and second conductive features and is in contact with a sidewall portion of at least the second conductive feature;
• and
• a third conductive feature extending through the second dielectric material, wherein at least a portion of the third conductive feature is within the space and is in contact with a second sidewall portion of the first conductive feature, and wherein:
• the first conductive feature, the second conductive feature and the first dielectric material are between the second dielectric material and a third dielectric material;
• the third conductive feature is separated from the third dielectric material by the first dielectric material;
• a surface of the first and second conductive features is planar with a surface of the first dielectric material;
• and
• the surfaces of the first and second conductive features that are planar with a surface of the first dielectric material are in contact with the third dielectric material.

An integrated circuit (IC) structure, comprising:

• a first conductive feature laterally adjacent to a second conductive feature with a space there between;
• a first dielectric material within the space and in contact with a first sidewall portion of at least the first conductive feature;
• a second dielectric material over the first dielectric material;
• one or more fins over the second dielectric material, wherein the one or more fins comprise a semiconductor material;
• a device terminal interconnect coupled to the one or more fins, wherein the device terminal interconnect comprises one or more metals, and wherein the device terminal interconnect comprises one or more overlapping portions that extend laterally beyond a sidewall of the one or more fins;
• and
• a conductive via that extends through the second dielectric material, wherein the conductive via is in contact with the first dielectric material within the space, and wherein the conductive via couples the device terminal interconnect to at least a sidewall portion of the first conductive feature.