Semiconductor chip including low-k dielectric layer

A semiconductor chip comprising:

• a device layer on a substrate, the device layer including a plurality of semiconductor devices;
• a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure;
• an upper inter-wiring dielectric layer on the lower inter-wiring dielectric layer;
• an isolation recess arranged along the entirety of an edge of the substrate and extending from a top surface of the upper inter-wiring dielectric layer at least to the same level as a bottom surface of the lower inter-wiring dielectric layer;
• a cover dielectric layer filling the isolation recess, covering at least a portion of the top surface of the upper inter-wiring dielectric layer, and having a step portion along at least a portion of the edge of the substrate;
• and
• a groove or a protrusion in a bottom surface of the step portion,
• wherein the cover dielectric layer includes a sub cover dielectric layer conformally covering a side surface of the lower inter-wiring dielectric layer, a top surface of the upper inter-wiring dielectric layer, and inner and bottom surfaces of the isolation recess.

A semiconductor chip comprising:

• a device layer on a substrate that has four sides which form a rectangular shape in a plan view, the device layer including a plurality of semiconductor devices;
• a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure;
• an upper inter-wiring dielectric layer on the lower inter-wiring dielectric layer;
• an isolation recess arranged along the entirety of an edge of the substrate and extending from a top surface of the upper inter-wiring dielectric layer at least to the same level as a bottom surface of the lower inter-wiring dielectric layer;
• a pad pattern on the upper inter-wiring dielectric layer and a pad via passing through the upper inter-wiring dielectric layer, the pad via electrically connecting the pad pattern to the wiring structure;
• an upper cover dielectric layer filling the isolation recess, covering at least a portion of the top surface of the upper inter-wiring dielectric layer, and having a step portion along at least one of the four sides of the substrate at a level that is higher than a top surface of the lower inter-wiring dielectric layer;
• and
• a groove or a protrusion in a bottom surface of the step portion, along at least one of the four sides of the substrate.