Embedded die packaging for power semiconductor devices

An embedded die package comprising a laminated body and a die, comprising a power semiconductor device, embedded within the laminated body, wherein:

• the die comprises a patterned layer of conductive metallization on a front-side of the die providing electrical contact areas of the power semiconductor device, and a thermal contact area on a back-side of the die;
• and
• a layer stack of the laminated body comprises:
• a core comprising at least one dielectric layer which embeds the die;
• a first dielectric build-up layer on a first side of the core;
• a first conductive layer on the first dielectric build-up layer;
• the first conductive layer being patterned to define interconnect areas;
• the interconnect areas of the first conductive layer being connected by electrically conductive vias to respective electrical contact areas of the power semiconductor device;
• and
• an outer dielectric build-up layer extending over the first dielectric build-up layer and first conductive layer,
• the outer dielectric build-up layer laterally electrically isolating the interconnect areas of the first conductive layer in a region extending over the die between said interconnect areas and vertically separating said region from an external surface of the laminated body;
• and
• a leadframe embedded within the core and surrounding the die, the leadframe providing a thermal pad in thermal contact with the thermal contact area on the back-side of the die.

An embedded die package comprising a laminated body and a die comprising a power semiconductor device, embedded within the laminated body, wherein:

• the power semiconductor device comprising a lateral power transistor, the die comprising a patterned layer of conductive metallization on a front-side of the die providing electrical contact areas for a source, drain and gate of the lateral power transistor, and a thermal contact area on a back-side of the die;
• and
• a layer stack of the laminated body comprises:
• a core comprising at least one dielectric layer which embeds the die;
• a first dielectric build-up layer on a first side of the core;
• a first conductive layer on the first dielectric build-up layer;
• the first conductive layer being patterned to define interconnect areas for the source, drain and gate of the lateral power transistor;
• the source, drain and gate interconnect areas of the first conductive layer being connected by electrically conductive vias to respective source, drain and gate contact areas of the power semiconductor device;
• and
• an outer dielectric build-up layer extending over the first dielectric build-up layer and first conductive layer,
• the outer dielectric build-up layer laterally electrically isolating the source and drain interconnect areas of the first conductive layer in a region extending over the die between said source and drain interconnect areas and vertically separating said region from an external surface of the laminated body.

An embedded die package comprising a laminated body and a die comprising a power semiconductor device, embedded within the laminated body, wherein:

• the power semiconductor device comprising a lateral power transistor, the die comprising a patterned layer of conductive metallization on a front-side of the die providing electrical contact areas for a source, drain and gate of the lateral power transistor, and a thermal contact area on a back-side of the die;
• and
• a layer stack of the laminated body comprises:
• a core comprising at least one dielectric layer which embeds the die;
• a first dielectric build-up layer on a first side of the core;
• a first conductive layer on the first dielectric build-up layer;
• the first conductive layer being patterned to define interconnect areas for the source, drain and gate of the lateral power transistor;
• the source, drain and gate interconnect areas of the first conductive layer being connected by electrically conductive vias to respective source, drain and gate contact areas of the power semiconductor device;
• and
• an outer dielectric build-up layer extending over the first dielectric build-up layer and first conductive layer,
• the outer dielectric build-up layer laterally electrically isolating the source and drain interconnect areas of the first conductive layer in a region extending over the die between said source and drain interconnect areas and vertically separating said region from an external surface of the laminated body;
• and
• wherein the core comprises a leadframe embedded within the core and supporting the die, the leadframe providing a thermal pad in thermal contact with the thermal contact area on the back-side of the die.