Chip package

A chip package, comprising:

• a heat-dissipating device;
• a first thermal interface material layer disposed on the heat-dissipating device, wherein the first thermal interface material layer has a thickness between 100 μm and 300 μm;
• a second thermal interface material layer covering a top surface of the first thermal interface material layer, the second thermal interface material layer comprising a top surface and a bottom surface opposite to the top surface, wherein an area of the top surface of the first thermal interface material layer is equal to an area of the bottom surface of the second thermal interface material layer, and the area of the top surface of the first thermal interface material layer is greater than an area of a top surface of the second thermal interface material layer;
• a patterned circuit layer disposed on the first thermal interface material layer, wherein the first thermal interface material layer is located between the patterned circuit layer and the heat-dissipating device;
• a chip disposed on the patterned circuit layer and electrically connected to the patterned circuit layer;
• and
• an insulating encapsulant covering the chip, the patterned circuit layer, and the first thermal interface material layer.