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US 11,776,856 B2Granted
Nanosheet transistors with different gate materials in same stack and method of making
AssigneeNXP B.V.
InventorsMark Douglas Hall, Tushar Praful Merchant, Anirban Roy
Life of this patent
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Abstract
A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (11-14, 17-20) which are separated from one another by a barrier oxide layer (15) and which are separately processed to form bottom gate electrodes having a first gate structure (40A-B) in the bottom Si/SiGe superlattice structures and to form top gate electrodes having a second, different gate structure (46A-B) in the top Si/SiGe superlattice structures.
Claims11
A method for forming a semiconductor device comprising:
- providing a stack of alternating semiconductor layers on a substrate, the stack comprising a plurality of first semiconductor layers interspersed in alternating fashion with a plurality of second semiconductor layers;
- selectively etching the stack of alternating semiconductor layers to form a transistor stack on the substrate;
- and
- processing the transistor stack to form a first set of gate electrode structures having a first gate structure between a first subset of the plurality of first semiconductor layers and to form a second set of gate electrode structures having a second, different gate structure between a second subset of the plurality of first semiconductor layers, where the second set of gate electrode structures is formed over the first set of gate electrode structures in the transistor stack;
- where processing the transistor stack to form the first set of gate electrode structures comprises:
- processing the transistor stack to form first remnant second semiconductor layers in at least a bottom portion of the transistor stack;
- selectively removing the first remnant second semiconductor layers from the transistor stack, thereby forming first gate electrode openings in the transistor stack;
- and
- sequentially depositing a first gate dielectric layer and first conductive gate layer in the first gate electrode openings, thereby forming the first set of gate electrode structures which replace the first remnant second semiconductor layers in the transistor stack;
- and
- where processing the transistor stack to form the second set of gate electrode structures comprises:
- sealing the bottom portion of the transistor stack with a dielectric layer;
- selectively removing the first gate dielectric layer and first conductive gate layer from a top portion of the transistor stack, thereby forming second gate electrode openings in the top portion of the transistor stack;
- and
- sequentially depositing a second gate dielectric layer and second conductive gate layer in the second gate electrode openings, thereby forming the second set of gate electrode structures in the top portion of the transistor stack.
12 more elements
A method for forming a semiconductor device comprising:
- providing a nanosheet stack on a substrate comprising a bottom superlattice structure and a top superlattice structure separated from one another by a barrier insulator layer, where each of the bottom and top superlattice structures comprises alternating silicon and silicon germanium nanosheet layers;
- selectively etching the nanosheet stack to form a nanosheet transistor stack on the substrate;
- processing the nanosheet transistor stack to form first remnant silicon germanium nanosheet layers in the bottom and top superlattice structures;
- forming first and second epitaxial source/drain semiconductor regions adjacent, respectively, to the bottom and top superlattice structures, where the first and second epitaxial source/drain semiconductor regions are electrically isolated from one another by an insulating layer;
- selectively processing the nanosheet transistor stack to form gate electrodes having a first gate structure comprising a first gate dielectric layer and first conductive gate layer which replace the first remnant silicon germanium nanosheet layers in the bottom and top superlattice structures, thereby forming a bottom nanosheet transistor comprising the gate electrodes having the first gate structure, the silicon nanosheet layers from the bottom superlattice structure, and the first epitaxial source/drain semiconductor regions;
- forming a protective structure to protect the bottom nanosheet transistor from subsequent processing;
- and
- selectively processing the nanosheet transistor stack to form top gate electrodes having a second, different gate structure comprising a second gate dielectric layer and second conductive gate layer which replaces the first gate dielectric layer and first conductive gate layer in the top superlattice structure, thereby forming a top nanosheet transistor comprising the top gate electrodes, the silicon nanosheet layers from the top superlattice structure, and the second epitaxial source/drain semiconductor regions.
5 more elements
Dependencies are inferred from the claim text.