Semiconductor device with reduced loading effect

A method for forming a semiconductor structure, comprising:

• depositing a dielectric layer on a substrate;
• depositing a patterning layer on the dielectric layer;
• performing a first etching process on the patterning layer to form a first plurality of blocks, wherein portions of the dielectric layer are exposed between adjacent blocks of the first plurality of blocks;
• performing a second etching process on the portions of the dielectric layer to form a second plurality of blocks under the first plurality of blocks;
• performing a third etching process on the second plurality of blocks to decrease a width of each block of the second plurality of blocks;
• and
• etching the substrate using the first and second pluralities of blocks to form a plurality of fin structures.

A method, comprising:

• disposing a lower patterning layer on a dielectric layer;
• disposing an upper patterning layer on the lower patterning layer;
• performing a first etching process on the upper patterning layer to form a patterned upper patterning layer, wherein the patterned upper patterning layer comprises a first region with a first pattern density and a second region with a second pattern density that is lower than the first pattern density;
• performing a second etching process on the lower patterning layer to form a patterned lower patterning layer, wherein the patterned lower patterning layer comprises a first plurality of blocks in the first region and a second plurality of blocks in the second region, wherein performing the second etching process comprises applying a substrate voltage bias to the dielectric layer and performing a first plasma etching process;
• and
• performing a third etching process on the first and second pluralities of blocks at respective first and second etching rates, wherein the first etching rate is lower than the second etching rate, and wherein performing the third etching process comprises performing a second plasma etching process without the substrate voltage bias.