Through silicon via fabrication

A process comprising:

• depositing a top mask onto a silicon wafer, the top mask comprising a first silicon dioxide layer;
• depositing a bottom mask onto the bottom of the silicon wafer;
• photopatterning a through silicon via pattern and etching a through silicon via into the top mask;
• etching the through silicon via, using the through silicon via pattern, through the silicon wafer;
• growing a second thermal silicon dioxide layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via;
• etching the second thermal silicon dioxide layer;
• growing a third thermal silicon dioxide layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via;
• depositing a plating seed layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via;
• electroplating a copper layer in the through silicon via;
• depositing a fourth silicon dioxide layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via;
• etching the fourth silicon dioxide layer;
• depositing a fifth silicon dioxide layer on the top of the silicon wafer, the bottom of the silicon wafer, and the through silicon via;
• etching the fifth silicon dioxide layer;
• depositing a sixth silicon dioxide layer on the top of the silicon wafer and the bottom of the silicon wafer;
• chemomechanically polishing (CMP) the sixth silicon dioxide layer down to the copper layer;
• and
• chemomechanically polishing the copper layer.