Vertical interconnection structure and manufacturing method thereof, packaged chip, and chip packaging method
AssigneeHuawei Technologies Co., Ltd.
InventorsXiaoyun Wei, Yong Yang, Chaojun Deng
Life of this patent
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Abstract
Embodiments of the application provide a vertical interconnection structure and a manufacturing method thereof, a packaged chip, and a chip packaging method. Conductive pillars are formed on a first surface of a substrate. A first insulated support layer wrapping the conductive pillars is formed on the first surface of the substrate. The conductive pillars are located in the first insulated support layer. An upper surface of the conductive pillar that is away from the substrate is not covered by the first insulated support layer. Then the substrate is removed.
Claims17
A method for manufacturing a vertical interconnection structure, comprising:
- forming conductive pillars on a first surface of a substrate;
- forming a first insulated support layer on the first surface, wherein the conductive pillars are located in the first insulated support layer, the first insulated support layer comprises at least one of the following materials:
- amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, boron nitride, silicon dioxide, aluminum nitride, and diamond, and wherein an upper surface of a conductive pillar that is away from the substrate is not covered by the first insulated support layer;
- removing the substrate;
- and
- before the forming the first insulated support layer on the first surface;
- forming a barrier layer, wherein the barrier layer covers a surface of the conductive pillar, and
- forming a dielectric layer on a surface of the barrier layer after the barrier layer is formed.
A vertical interconnection structure, wherein the vertical interconnection structure is manufactured by using the following operations:
- forming conductive pillars on a first surface of a substrate;
- forming a first insulated support layer on the first surface, wherein the conductive pillars are located in the first insulated support layer, the first insulated support layer comprises at least one of the following materials:
- amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, boron nitride, silicon dioxide, aluminum nitride, and diamond, and wherein an upper surface of a conductive pillar that is away from the substrate is not covered by the first insulated support layer;
- removing the substrate;
- and
- before the forming the first insulated support layer on the first surface;
- forming a barrier layer, wherein the barrier layer covers a surface of the conductive pillar, and
- forming a dielectric layer on a surface of the barrier layer after the barrier layer is formed.
A chip packaging method, comprising:
- forming conductive pillars on a first surface of a substrate;
- forming a first insulated support layer on the first surface, wherein the conductive pillars are located in the first insulated support layer, the first insulated support layer comprises at least one of the following materials:
- amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, boron nitride, silicon dioxide, aluminum nitride, and diamond, and wherein an upper surface of a conductive pillar that is away from the substrate is not covered by the first insulated support layer;
- disposing a first die on a surface of the first insulated support layer that is away from the substrate;
- removing the substrate;
- and
- before the forming the first insulated support layer on the first surface,
- forming a barrier layer, wherein the barrier layer covers a surface of the conductive pillar, and
- forming a dielectric layer on a surface of the barrier layer after the barrier layer is formed.
A packaged chip, wherein the packaged chip is packaged by using the following operations:
- forming conductive pillars on a first surface of a substrate;
- forming a first insulated support layer on the first surface, wherein the conductive pillars are located in the first insulated support layer, the first insulated support layer comprises at least one of the following materials:
- amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, boron nitride, silicon dioxide, aluminum nitride, and diamond, and an upper surface of a conductive pillar that is away from the substrate is not covered by the first insulated support layer;
- disposing a first die on a surface of the first insulated support layer that is away from the substrate;
- removing the substrate;
- and
- before the forming the first insulated support layer on the first surface;
- forming a barrier layer, wherein the barrier layer covers a surface of the conductive pillar, and
- forming a dielectric layer on a surface of the barrier layer after the barrier layer is formed.
Dependencies are inferred from the claim text.