Fin patterning to reduce fin collapse and transistor leakage

A method for creating three-dimensional devices, comprising:

• forming a fin hardmask pattern on a silicon substrate;
• using a fin etch process to create at least one fin structure on the silicon substrate;
• and
• decreasing a width of the at least one fin structure by applying one or more iterations of a self-limiting fin etch process, wherein each iteration of the self-limiting fin etch process decreases the width of the at least one fin structure to a desired width by only one atomic layer, and wherein the desired width prevents fin collapse and current leakage in the at least one fin structure.

A method for creating a fin structure on a silicon substrate, comprising:

• forming a fin hardmask pattern on the silicon substrate, wherein a feature on the fin hardmask pattern comprises a thermal oxide layer grown on the silicon substrate, a silicon nitride layer disposed on the thermal oxide layer, and an oxide layer disposed on the silicon nitride layer;
• using a fin etch process to create the fin structure on the silicon substrate corresponding to the feature on the fin hardmask pattern;
• and
• decreasing a width of the fin structure by applying one or more iterations of a self-limiting fin etch process, wherein each iteration of the self-limiting fin etch process decreases the width of the at least one fin structure to a desired width by only one atomic layer, and wherein the desired width prevents fin collapse and current leakage in the at least one fin structure.