Back to results
US 11,776,653 B2Granted
Memory device
AssigneeSK hynix Inc.
InventorsJi Hwan Park, Sang Muk Oh, Byung Kuk Yoon
Life of this patent
Estimating the term…
Abstract
Disclosed is a memory device including an error logic unit suitable for determining whether an error is present in command signals to generate a command error signal; a replica delay circuit suitable for replicating a delay value of the error logic unit and generating an input strobe signal by delaying a strobe signal of the command signals; an output strobe signal generation circuit suitable for generating an output strobe signal activated after a command error latency elapses from a time point at which the command signals are received; and a pipe circuit suitable for receiving and storing the command error signal in response to the input strobe signal and outputting the stored command error signal in response to the output strobe signal.
Claims16
A memory device comprising:
- an error logic unit configured to determine whether an error is present in command signals to generate a command error signal;
- a replica delay circuit configured to replicate a delay value of the error logic unit and generate an input strobe signal by delaying a strobe signal of the command signals;
- an output strobe signal generation circuit configured to generate an output strobe signal activated after a command error latency elapses from a time point at which the command signals are received;
- and
- a pipe circuit configured to receive and store the command error signal in response to the input strobe signal and output the stored command error signal in response to the output strobe signal.
2 more elements
A memory device comprising:
- an error logic unit configured to determine whether an error is present in data to generate a data error signal;
- a replica delay circuit configured to replicate a delay value of the error logic unit and generate an input strobe signal by delaying a strobe signal of the data;
- an output strobe signal generation circuit configured to generate an output strobe signal activated after a data error latency elapses from a time point at which a write command corresponding to the data is received;
- and
- a pipe circuit configured to receive and store the data error signal in response to the input strobe signal and output the stored data error signal in response to the output strobe signal.
2 more elements
A memory device comprising:
- a command error logic unit configured to determine whether an error is present in command signals to generate a command error signal;
- a command replica delay circuit configured to replicate a delay value of the command error logic unit and generate a command input strobe signal by delaying a strobe signal of the command signals;
- a command output strobe signal generation circuit configured to generate a command output strobe signal activated after a command error latency elapses from a time point at which the command signals are received;
- a command pipe circuit configured to receive and store the command error signal in response to the command input strobe signal and output the stored command error signal in response to the command output strobe signal;
- a data error logic unit configured to determine whether an error is present in data, and generating a data error signal;
- a data replica delay circuit configured to replicate a delay value of the data error logic unit and generate a data input strobe signal by delaying a strobe signal of the data;
- a data output strobe signal generation circuit configured to generate a data output strobe signal activated after a data error latency elapses from a time point at which a write command corresponding to the data is received;
- and
- a data pipe circuit configured to receive and store the data error signal in response to the data input strobe signal and output the stored data error signal in response to the data output strobe signal.
6 more elements
A memory device comprising:
- a plurality of channel regions;
- a plurality of data input pads and at least one test data input pad;
- a plurality of data input circuits corresponding to the respective channel regions and each configured to transfer data from the plurality of data input pads to a corresponding channel region of the channel regions;
- and
- a test control circuit configured to select at least one of the plurality of data input circuits according to test mode information and control the selected data input circuit to transmit the data to a corresponding channel region of the channel regions, during a test operation,
- wherein at least one of the plurality of channel regions includes:
- an error logic unit configured to determine whether an error is present in the data transmitted thereto to generate a data error signal;
- a replica delay circuit configured to replicate a delay value of the error logic unit and generate an input strobe signal by delaying a strobe signal of the data transmitted thereto;
- an output strobe signal generation circuit suitable for generating an output strobe signal activated after a data error latency elapses from a time point at which a write command corresponding to the data transmitted thereto is received;
- and
- a pipe circuit configured to receive and store the data error signal in response to the input strobe signal and output the stored data error signal in response to the output strobe signal.
8 more elements
Dependencies are inferred from the claim text.