Controlling memory including managing a correction value table

A method of controlling a memory device, the memory device including first and second memory cells, a first word line, and first and second bit lines, the first memory cell and the second memory cell being stacked above a substrate, the first memory cell being provided in a first layer, the second memory cell being provided in a second layer, the first word line being coupled to the first memory cell and the second memory cell, the first bit line being coupled to the first memory cell, and the second bit line being coupled to the second memory cell, the method comprising:

• managing a correction value table, the correction value table storing a first correction value of a read voltage associated with the first layer and a second correction voltage of a read voltage associated with the second layer;
• selecting the first word line and instructing the memory device to read first-page data which is a set of first-bit data;
• performing hard bit decoding on the first-page data read from the memory device;
• calculating a first shift amount of a read voltage optimized for the first layer and a second shift amount of a read voltage optimized for the second layer based on the read first-page data and the first-page data corrected by the hard-bit decoding, and
• updating the first correction value and the second correction value of the correction value table based on the first shift amount and the second shift amount.