Circuit for testing memory

A test circuit for testing a memory, an input of the memory being coupled to a register, and the register being coupled to a logic circuit, the test circuit comprising:

• a first test register group, comprising at least one test register;
• a second test register group, comprising at least one test register;
• a first multiplexer, coupled between the first test register group and the register;
• and
• a plurality of second multiplexers, coupled between the second test register group and the register;
• wherein the first test register group comprises a first test register, a second test register, a third test register, and a fourth test register that are electrically connected in sequence, and an output of the third test register is an input of the second test register;
• and
• wherein the first test register, the second test register, the third test register, and the fourth test register store a first bit value, a second bit value, a third bit value, and a fourth bit value, respectively, the first bit value and the second bit value correspond to a write operation of the memory, and the third bit value and the fourth bit value correspond to a read operation of the memory.