Systems and methods for distributing programming speed among blocks with different program-erase cycle counts

A memory system for performing a programming operation in a multi-plane programming system, the memory system comprising:

• a memory controller configured to cause a shared programming voltage line to:
• receive, at a first word line of a first block, a voltage equal to a programming voltage plus a positive delta voltage, wherein the first block is located in a first plane and has undergone a first number of program-erase cycles;
• receive, at a second word line of a second block, the voltage, wherein the second block is located in a second plane and has undergone a second number of program-erase cycles, wherein the second number of program-erase cycles is less than the first number of program-erase cycles;
• and
• receive, at a first bit line, the positive delta voltage, wherein the first bit line crosses the first word line.

A non-volatile memory system, comprising:

• a first block and a second block;
• a memory controller configured to:
• apply, at a first word line of the first block, a voltage equal to a programming voltage plus a delta voltage, wherein the first block is located in a first plane and has undergone a first number of program-erase cycles;
• apply, at a second word line of the second block, the voltage, wherein the second block is located in a second plane and has undergone a second number of program-erase cycles, wherein the second number of program-erase cycles is less than the first number of program-erase cycles;
• and
• apply, at a first bit line, the delta voltage, wherein the first bit line crosses the first word line, and wherein the delta voltage is based on the first number of program-erase cycles.