Data conversion with data path circuits for use in double sense amp architecture with fractional bit assignment in non-volatile memory structures

A memory controller, comprising:

• a first communication pathway configured to couple to a non-volatile memory structure;
• and
• the memory controller configured to:
• initiate a two-dimensional fractional number of bits-per-cell programming scheme with respect to a plurality of memory cells of the memory structure, the memory structure comprising:
• a first memory array comprising a first population of the plurality of memory cells and associated peripheral circuitry, wherein the associated peripheral circuitry is disposed below the first population of the plurality of memory cells;
• a second memory array:
• positioned above the first memory array;
• and
• comprising a second population of the plurality of memory cells and associated peripheral circuitry, wherein the associated peripheral circuitry is disposed above the second population of the plurality of memory cells;
• a data bus tap electrically coupling the first memory array and the second memory array;
• store input data:
• in a first set of data latches associated with the first memory array;
• and
• in a second set of data latches associated with the second memory array;
• convert the input data stored in the:
• first set of data latches and the second set of data latches using data conversion logic implemented by a data path circuit of the peripheral circuitry associated with the first memory array;
• and
• first set of data latches and the second set of data latches using data conversion logic implemented by a data path circuit of the peripheral circuitry associated with the second memory array;
• and
• rewrite the converted data to:
• the first set of data latches;
• and
• the second set of data latches.

A non-volatile memory system, comprising:

• a memory structure, comprising:
• a first memory array comprising a first population of a plurality of memory cells of the memory structure and associated peripheral circuitry, wherein the associated peripheral circuitry is disposed below the first population of the plurality of memory cells;
• a second memory array:
• positioned above the first memory array;
• and
• comprising a second population of the plurality of memory cells and associated peripheral circuitry, wherein the associated peripheral circuitry is disposed above the second population of the plurality of memory cells;
• and
• a data bus tap electrically coupling the first memory array and the second memory array;
• and
• a memory controller coupled to the memory structure and:
• initiating a two-dimensional fractional number of bits-per-cell programming scheme with respect to the plurality of memory cells;
• storing input data:
• in a first set of data latches associated with the first memory array;
• and
• in a second set of data latches associated with the second memory array;
• converting the input data stored in the:
• first set of data latches and the second set of data latches using data conversion logic implemented by a data path circuit of the peripheral circuitry associated with the first memory array;
• and
• first set of data latches and the second set of data latches using data conversion logic implemented by a data path circuit of the peripheral circuitry associated with the second memory array;
• and
• rewriting the converted data to:
• the first set of data latches;
• and
• the second set of data latches.