Semiconductor memory device

A semiconductor memory device comprising:

• a memory transistor;
• and
• a plurality of wirings connected to the memory transistor, wherein
• the memory transistor includes:
• a semiconductor layer;
• a gate electrode opposed to the semiconductor layer;
• and
• a gate insulating film disposed between the semiconductor layer and the gate electrode, wherein
• the plurality of wirings include:
• a first wiring connected to the semiconductor layer;
• a second wiring connected to the semiconductor layer;
• and
• a third wiring connected to the gate electrode, wherein
• the gate insulating film includes oxygen (O) and hafnium (Hf) and has an orthorhombic crystalline structure, wherein
• the semiconductor memory device is configured to execute a write operation, an erase operation, and a first read operation,
• in the write operation, a write voltage in a first polarity is supplied between the third wiring and at least one of the first wiring or the second wiring,
• in the erase operation, an erase voltage in a second polarity is supplied between the third wiring and at least one of the first wiring or the second wiring, the second polarity being different from the first polarity,
• in the first read operation, the erase voltage or a voltage having a larger amplitude than an amplitude of the erase voltage in the second polarity is supplied between the third wiring and at least one of the first wiring or the second wiring.