Integrated circuit device
AssigneeSamsung Electronics Co., Ltd.
InventorsJang-Gn Yun, Jae-Duk Lee
Life of this patent
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Abstract
An integrated circuit device includes channel structures extending from a substrate in a vertical direction, memory cell strings disposed along the plurality of channel structures, gate lines spaced apart from one another in the vertical direction and including erase control lines and string selection lines, and driving transistors including erase control driving transistors connected to the erase control lines and string selection driving transistors connected to the string selection lines.
Claims20
An integrated circuit device comprising:
- channel structures extending in a vertical direction from a substrate;
- gate electrodes vertically stacked on the substrate, intersecting the channel structures, and extending in a first horizontal direction;
- a first stack structure including a first group of the gate electrodes;
- a second stack structure on the first stack structure, the second stack structure including a second group of the gate electrodes;
- and
- an erase control driving transistor,
- wherein at least two of the gate electrodes respectively function as erase control lines, the erase control lines are commonly connected to the erase control driving transistor.
An integrated circuit device comprising:
- a plurality of channel structures extending in a vertical direction from a main surface of a substrate;
- a plurality of gate lines spaced apart from one another in the vertical direction and including erase control lines and string selection lines;
- a first stack structure including a first group of the plurality of gate lines;
- a second stack structure on the first stack structure, the second stack structure including a second group of the plurality of gate lines;
- and
- a plurality of driving transistors including erase control driving transistors connected to the erase control lines and,
- wherein at least two gate lines spaced apart from one another in a horizontal direction with respect to the main surface of the substrate among the plurality of gate lines are commonly connected to one of the plurality of driving transistors.
An integrated circuit device comprising:
- channel structures extending in a vertical direction from a substrate;
- bit lines respectively connected to the channel structures and extending in a first horizontal direction;
- a peripheral circuit region disposed at a level lower than that of the channel structures;
- gate electrodes vertically stacked on the substrate, intersecting the channel structures, and extending in a second horizontal direction over the substrate;
- a first stack structure including a first group of the gate electrodes;
- and
- a second stack structure on the first stack structure, the second stack structure including a second group of the gate electrodes;
- wherein the gate electrodes include word lines, erase control lines, and string selection lines,
- each one of the first stack structure and the second stack structure includes at least one of the erase control lines, and
- at least two of the erase control lines are electrically connected to each other by a common connection wiring line.
Dependencies are inferred from the claim text.