Memory device performing incremental step pulse program operation and operating method thereof
AssigneeSK hynix Inc.
InventorHyung Jin Choi
Life of this patent
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Abstract
A memory device comprises a memory cell array and a control circuit. The control circuit applies a pass voltage to each of a selected and unselected word line from a first to second time point whenever a program loop is performed once. Then, the control circuit applies a program voltage to the selected word line and the pass voltage to the unselected word line from the second to third time point, performs a bit line precharge operation from a fourth time point ahead of the first time point to the second time point when a first program loop is performed, and performs the bit line precharge operation from the fourth time point to a fifth time point, which is the same as or ahead of the first time point, when the other program loops are performed.
Claims13
A memory device comprising:
- a memory cell array including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines;
- and
- a control circuit suitable for performing a program operation of repeatedly performing a program loop until programming is completed according to an incremental step pulse program (ISPP) scheme, the program loop including:
- applying a pass voltage to each of a first word line selected as a program target and a second word line unselected among the plurality of word lines from a first time point to a second time point, and
- applying a program voltage to the first word line and the pass voltage to the second word line from the second time point to a third time point,
- wherein the control circuit performs the program operation by:
- performing a bit line precharge operation of precharging each of the plurality of bit lines to a predetermined potential level from a fourth time point ahead of the first time point to the second time point during a first program loop, and
- performing the bit line precharge operation from the fourth time point to a fifth time point, which is the same as or ahead of the first time point, during each of remaining program loops except for the first program loop.
An operating method of a memory device including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines, the operating method comprising:
- a program loop operation of applying a pass voltage to each of a first word line selected as a program target and a second word line unselected among the plurality of word lines from a first time point to a second time point after a starting time point, and applying a program voltage to the first word line and the pass voltage to the second word line from the second time point to a third time point;
- and
- a repetition operation of repeatedly performing the program loop operation according to an incremental step pulse program (ISPP) scheme until programming is completed,
- wherein the repetition operation includes:
- a first precharge operation of performing a bit line precharge operation of precharging each of the plurality of bit lines to a predetermined potential level from a fourth time point ahead of the first time point to the second time point during a first program loop operation first repeated in the repetition operation;
- and
- a second precharge operation of performing the bit line precharge operation from the fourth time point to a fifth time point, which is the same as or ahead of the first time point, during a subsequent program loop operation repeated after the first program loop operation in the repetition operation.
A method for operating a memory device, the method comprising:
- performing, on a memory cell array, a program operation including initial and subsequent program loops according to an incremental step pulse program (ISPP) scheme,
- wherein the initial program loop includes precharging a bit line coupled to the array before and while applying a pass voltage to all word lines coupled to the array,
- wherein the subsequent program loop includes precharging the bit line before the applying, and
- wherein the precharging in the initial program loop takes a greater time amount than the precharging in the subsequent program loop.
Dependencies are inferred from the claim text.