Boost-assisted memory cell selection in a memory array
AssigneeMicron Technology, Inc.
InventorsMingdong Cui, Hongmei Wang, Hari Giduturi
Life of this patent
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Abstract
Systems, methods, and apparatus related to selecting memory cells in a memory array of a memory device. In one approach, bias circuitry generates a voltage on an access line used to select a memory cell for programming. During programming, a controller connects a boost capacitor to the access line by controlling a switch. Connecting the boost capacitor causes an increase in the rate of discharge of the access line (e.g., discharge of a word line to a negative voltage). After programming, the controller disconnects the boost capacitor from the access line, and the boost capacitor is pre-charged in preparation for a next programming operation (e.g., on the same or a different memory cell).
Claims27
An apparatus comprising:
- bias circuitry electrically connected to an access line used to access a memory cell of a memory array, the bias circuitry configured to generate a voltage on the access line;
- at least one capacitor configured to boost the voltage on the access line when accessing the memory cell, wherein boosting the voltage comprises lowering the voltage on the access line;
- at least one switch configured to electrically connect the capacitor to the bias circuitry, wherein the switch is in an on state when the capacitor is boosting the voltage;
- and
- pre-charging circuitry configured to pre-charge the capacitor, wherein the switch is in an off state when the capacitor is being pre-charged in preparation for boosting the voltage.
An apparatus comprising:
- a capacitor;
- bias circuitry electrically connected to an access line used to access a memory cell in a memory array, the bias circuitry configured to generate a voltage on the access line;
- a switch configured to electrically connect the capacitor to the bias circuitry, the capacitor being separated from the access line, wherein:
- the capacitor is configured to boost the voltage on the access line after the bias circuitry starts to generate the voltage, wherein boosting the voltage comprises lowering the voltage on the access line;
- and
- the switch is in an on state when the capacitor is boosting the voltage, and the switch is in an off state when the capacitor is being pre-charged;
- and
- pre-charging circuitry configured to pre-charge the capacitor after the capacitor has boosted the voltage on the access line.
A non-transitory computer-readable medium storing instructions which, when executed by a controller, cause the controller to:
- receive a write command from a host device;
- in response to receiving the write command, cause bias circuitry to generate a voltage on an access line used to program a memory cell of a memory array, wherein the bias circuitry is electrically connected to the access line;
- after the bias circuitry starts to generate the voltage on the access line, cause a capacitor to boost the voltage on the access line, wherein the capacitor is separated from the access line, wherein boosting the voltage comprises lowering the voltage on the access line;
- program the memory cell;
- and
- after the memory cell has been programmed, cause pre-charging circuitry to pre-charge the capacitor.
A method comprising:
- receiving, by a controller, a write command;
- in response to receiving the write command, causing, by the controller, bias circuitry to generate a voltage on an access line, wherein the bias circuitry is electrically connected to the access line and the access line is configured to program a memory cell of a memory array;
- boosting, using a capacitor, the voltage on the access line when programming the memory cell, wherein the capacitor is separated from the access line, wherein boosting the voltage comprises lowering the voltage on the access line;
- and
- after programming the memory cell, pre-charging the capacitor.
Dependencies are inferred from the claim text.