Memory system and memory device
AssigneeKioxia Corporation
InventorsNaomi Takeda, Masanobu Shirakawa, Akio Sugahara
Life of this patent
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Abstract
According to one embodiment, a memory system includes n memory cells, each capable of storing j bits of data; and a controller. The controller is configured to write a first portion of each of first data to n-th data from among n×j data with consecutive logical addresses to the n memory cells one by one. The first data has a lowest logical address among the n×j pieces of data. The first data to the n-th data have ascending consecutive logical addresses. The controller is configured to write the first portion of one of the first to n-th data as a first bit of the j bits, and write the first portion of another one of the first to n-th data except said one of the first to n-th data as a second bit of the j bits.
Claims14
A method of controlling a semiconductor memory device including a first plurality of memory cells, a second plurality of memory cells, a first word line coupled to the first plurality of memory cells and a second word line coupled to the second plurality of memory cells, the first plurality of memory cells and the second plurality of memory cells being capable of being read in parallel, each capable of storing n (where n is a natural number equal to or greater than 2) bits of data, the method comprising:
- writing first data to the first plurality of memory cells as an i-th bit of data of the n bits of data;
- writing second data to the second plurality of memory cells as a j-th bit of data of the n bits of data, a logical address corresponding to the first data being smaller than a logical address corresponding to the second data, the logical address corresponding to the first data and the logical address corresponding to the second data being consecutive;
- writing third data to a third plurality of memory cells as a k-th bit of data of the n bits of data, the third plurality of memory cells being one of the first plurality of memory cells and the second plurality of memory cells, the logical address corresponding to the second data being smaller than a logical address corresponding to the third data;
- and
- writing fourth data to a fourth plurality of memory cells as an l-th bit of data of the n bits of data, the fourth plurality of memory cells being one of the first plurality of memory cells and the second plurality of memory cells, the fourth plurality of memory cells being different from the third plurality of memory cells, the logical address corresponding to the third data being smaller than a logical address corresponding to the fourth data, the logical address corresponding to the third data and the logical address corresponding to the fourth data being consecutive, wherein
- j is a natural number different from i,
- k is a natural number different from l, and
- each of k and l is a natural number different from one of i and j.
Dependencies are inferred from the claim text.