US 11,776,621 B2Granted

Memory device for increasing write margin during write operation and reducing current leakage during standby operation and operation method thereof

AssigneeNational Chung Cheng University

InventorsJinn Shyan Wang, Chien Tung Liu, Chih Jung Liu

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Abstract

A memory device and an operation method thereof is disclosed. The memory device includes a SRAM cell and a power supply assist circuit connected to the SRAM cell. The power supply assist circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor receives a power supply voltage. The control terminals of the first transistor and the second transistor are connected to each other. The third transistor switches, in response to a first control signal, to connect the control terminal and the connect terminal of the second transistor. The fourth transistor switches, in response to a second control signal, to drive the control terminal of the second transistor to a system ground voltage. The fifth transistor switches, in response to a third control signal, to drive the control terminal of the first transistor to the power supply voltage.

Claims14

Dependent claims

A memory device comprising:

a static random access memory (SRAM) cell including:
a memory transistor configured to receive a first power supply voltage, wherein the first power supply voltage is substantially equal to a system power supply voltage;
and
a power supply voltage node for receiving a second power supply voltage or for not receiving a power supply voltage, wherein the second power supply voltage is substantially equal to or less than the first power supply voltage;
and
a power supply assist circuit including:
a first transistor connected to an internal voltage node and configured to receive the first power supply voltage;
a second transistor connected to the power supply voltage node of the SRAM cell and the internal voltage node and configured to receive an internal power supply voltage from the internal voltage node, wherein control terminals of the first transistor and the second transistor are connected together;
a third transistor configured to switch, in response to a first control signal, to connect the control terminal of the second transistor and a connect terminal of the second transistor connected to the power supply voltage node;
a fourth transistor configured to switch, in response to a second control signal, to drive the control terminal of the second transistor to a system ground voltage;
and
a fifth transistor configured to switch, in response to a third control signal, to drive the control terminal of the first transistor to the first power supply voltage.

9 more elements

A memory device comprising:

a memory array comprising static random access memory (SRAM) cells, wherein each of the SRAM cells includes:
a memory transistor configured to receive a first power supply voltage, wherein the first power supply voltage is substantially equal to a system power supply voltage;
and
a power supply voltage node for receiving a second power supply voltage or for not receiving a power supply voltage, wherein the second power supply voltage is substantially equal to or less than the first power supply voltage;
and
one or more power supply assist circuits, wherein the power supply assist circuit includes:
a first transistor connected to an internal voltage node and configured to receive the first power supply voltage;
a second transistor connected to the power supply voltage node of the SRAM cell and the internal voltage node and configured to receive an internal power supply voltage from the internal voltage node, wherein control terminals of the first transistor and the second transistor are connected together;
a third transistor configured to switch, in response to a first control signal, to connect the control terminal of the second transistor and a connect terminal of the second transistor connected to the power supply voltage node;
a fourth transistor configured to switch, in response to a second control signal, to drive the control terminal of the second transistor to a system ground voltage;
and
a fifth transistor configured to switch, in response to a third control signal, to drive the control terminal of the first transistor to the first power supply voltage.

9 more elements

Dependencies are inferred from the claim text.