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US 11,776,619 B2Granted
Techniques to couple high bandwidth memory device on silicon substrate and package substrate
AssigneeTahoe Research, Ltd.
InventorsChong J. Zhao, James A. McCall, Shigeki Tomishima, George Vergis, Kuljit S. Bains
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Abstract
Techniques to couple a high bandwidth memory device on a silicon substrate and a package substrate are disclosed. Examples include selectively activating input/out (I/O) or command and address (CA) contacts on a bottom side of a logic layer for the high bandwidth device based on a mode of operation. The I/O and CA contacts are for accessing one or more memory devices include in the high bandwidth memory device via one or more data channels.
Claims20
An apparatus comprising:
- a mode register to indicate a mode of operation for a high bandwidth memory stack device to include a plurality of memory devices stacked above a logic layer;
- and
- circuitry at the logic layer to execute logic, the logic to:
- read a value of the mode register;
- and
- cause, based on the value of the mode register, a portion of input/output (I/O) contacts on a bottom side of the logic layer to be inactive and a remaining portion of the I/O contacts to be active, the portion of I/O contacts arranged to receive or transmit I/O signals for one or more data channels to access the plurality of memory devices.
3 more elements
A method comprising:
- determining, via a mode register, a mode of operation for a high bandwidth memory stack device include a plurality of memory devices stacked above a logic layer;
- and
- causing, based on the determined mode of operation, a portion of input/output (I/O) contacts on a bottom side of the logic layer to be inactive and a remaining portion of the I/O contacts to be active, the portion of I/O contacts arranged to receive or transmit I/O signals for one or more data channels to access the plurality of memory devices.
A memory device comprising:
- a plurality of stacked memory dice;
- a mode register to indicate a mode of operation;
- and
- a logic layer located below the plurality of stacked memory dice, the logic layer to include
- circuitry to execute logic, the logic to:
- read a value of the mode register;
- and
- cause, based on the value of the mode register, a portion of input/output (I/O) contacts on a bottom side of the logic layer to be inactive and a remaining portion of the I/O contacts to be active, the portion of I/O contacts arranged to receive or transmit I/O signals for one or more data channels to access at least one memory array maintained on at least one memory die of the plurality of stacked memory die.
5 more elements
Dependencies are inferred from the claim text.