Application processors and electronic devices including the same

An electronic device comprising:

• a semiconductor memory device configured to store data;
• and
• an application processor configured to control the semiconductor memory device, wherein:
• the application processor includes:
• a memory interface connected to the semiconductor memory device through first data input/output (I/O) pads and second data I/O pads;
• and
• a memory controller configured to exchange the data with the semiconductor memory device by controlling the memory interface,
• the memory interface includes a training circuit configured to perform duty training of first data signals and second data signals which are based on the data, based on a reception control code set, by:
• adjusting a duty of each of the first data signals with respect to a first reference voltage, the first data signals received through the first data I/O pads;
• and
• adjusting a duty of each of the second data signals with respect to a second reference voltage, the second data signals received through the second data I/O pads.

An application processor comprising:

• a memory interface connected to a semiconductor memory device through first data input/output (I/O) pads and second data I/O pads;
• a memory controller configured to exchange data with the semiconductor memory device by controlling the memory interface;
• and
• an on-chip memory connected to the memory interface, wherein:
• the memory interface includes a training circuit configured to perform duty training of first data signals and second data signals, based on a reception control code set, by:
• adjusting a duty of each of the first data signals with respect to a first reference voltage, the first data signals received through the first data I/O pads;
• and
• adjusting a duty of each of the second data signals with respect to a second reference voltage, the second data signals received through the second data I/O pads,
• the memory interface includes:
• a data reception circuit connected to the first data I/O pads and the second data I/O pads, the data reception circuit including:
• first receivers, each configured to receive a respective one of the first data signals from the semiconductor memory device;
• and
• second receivers, each configured to receive a respective one of the second data signals from the semiconductor memory device;
• and
• a data transmission circuit connected to the first data I/O pads and the second data I/O pads, the data transmission circuit including:
• first transmitters, each configured to transmit a respective one of the first data signals to the semiconductor memory device;
• and
• second transmitters, each configured to transmit a respective one of the second data signals to the semiconductor memory device, and
• the training circuit is configured to:
• calculate eye opening values of an initial value through a final value of possible combinations of the reception control code set by sweeping the possible combinations from the initial value to the final value;
• and
• store the eye opening values in the on-chip memory with a table form.