Sequential SLC read optimization

A system comprising:

• a memory device;
• and
• a processing device, coupled to the memory device, and configured to perform operations comprising:
• receiving a plurality of read commands in a first order, each associated with different respective logical addresses;
• determining that a subset of the different respective logical addresses correspond to respective physical addresses associated with a first word line of the memory device;
• and
• executing the plurality of read commands in a second order, where in the second order, a subset of the plurality of read commands associated with the subset of the different respective logical addresses are executed sequentially.

A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operation comprising:

• receiving a plurality of read commands in a first order, each associated with different respective logical addresses;
• determining that a subset of the different respective logical addresses correspond to respective physical addresses associated with a first word line of a memory device;
• and
• executing the plurality of read commands in a second order, where in the second order, a subset of the plurality of read commands associated with the subset of the different respective logical addresses are executed sequentially.