DRAM, memory controller and associated training method
AssigneeMediatek Inc.
InventorsBo-Wei Hsieh, Ching-Yeh Hsuan, Shang-Pin Chen
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Abstract
A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.
Claims19
A memory controller generating plural signals to a memory, wherein the memory controller outputs a clock signal and command/address signals to the memory and receives a first sampled content or a second sampled content through a plurality of data signals from the memory in response to a control signal,
- wherein the memory controller is configured to program a specified bit of a mode register of the memory using the control signal,
- wherein the specified bit is a phase select bit and the mode register further includes a command bus training mode bit.
Dependencies are inferred from the claim text.