Memory-element-including semiconductor device

A memory-element-including semiconductor device comprising a dynamic flash memory cell and an SGT transistor, wherein

• the dynamic flash memory cell includes
• a first semiconductor pillar standing on a substrate in a direction perpendicular to the substrate,
• a first impurity layer connected to a bottom portion of the first semiconductor pillar,
• a second impurity layer disposed at or connected to a top portion of the first semiconductor pillar,
• a first gate insulating layer surrounding a lower portion of the first semiconductor pillar and being in contact with the first impurity layer,
• a second gate insulating layer being in contact with the first gate insulating layer and surrounding an upper portion of the first semiconductor pillar,
• a first gate conductor layer surrounding a part or an entirety of the first gate insulating layer,
• a second gate conductor layer surrounding a part or an entirety of the second gate insulating layer, and
• a first insulating layer disposed between the first gate conductor layer and the second gate conductor layer,
• the dynamic flash memory cell is configured to perform a memory write operation, a memory erase operation, and a memory read operation by controlling voltages to be applied to the first impurity layer, the second impurity layer, the first gate conductor layer, and the second gate conductor layer,
• the SGT transistor includes
• a second semiconductor pillar standing on the substrate in a direction perpendicular to the substrate,
• a second insulating layer surrounding a lower portion of the second semiconductor pillar,
• a third impurity layer disposed in a region of the second semiconductor pillar, the region being surrounded by an upper portion of the second insulating layer,
• a fourth impurity layer connected to an upper end of the second semiconductor pillar,
• a third gate insulating layer surrounding a region of the second semiconductor pillar, the region being between the third impurity layer and the fourth impurity layer, and
• a third gate conductor layer surrounding the third gate insulating layer, and
• bottom portions of the first semiconductor pillar and the second semiconductor pillar are disposed at the same position in the perpendicular direction, and top portions of the first semiconductor pillar and the second semiconductor pillar are disposed at the same position in the perpendicular direction.