Static random-access memory (SRAM) compute in-memory integration
AssigneeQUALCOMM Incorporated
InventorsXia Li, Jianguo Yao, Bin Yang
Life of this patent
Estimating the term…
Abstract
Certain aspects provide methods and apparatus for in-memory convolution computation. An example circuit for such computation generally includes a memory cell having a bit-line and a complementary bit-line and a computation circuit coupled to a computation input node of the circuit and at least one of the bit-line or the complementary bit-line. In certain aspects, the computation circuit comprises a counter, an NMOS transistor coupled to the memory cell, and a PMOS transistor coupled to the memory cell, drains of the NMOS and PMOS transistors being coupled to the counter.
Claims12
A circuit for in-memory computation, comprising:
- a memory cell having a bit-line and a complementary bit-line;
- and
- a computation circuit coupled to a computation input node of the circuit and at least one of the bit-line or the complementary bit-line, wherein:
- the computation circuit comprises a counter, a first n-type metal-oxide-semiconductor (NMOS) transistor coupled to the memory cell, and a first p-type metal-oxide-semiconductor (PMOS) transistor coupled to the memory cell, drains of the first NMOS and PMOS transistors being coupled to the counter;
- a gate of the first NMOS transistor is connected with the computation input node;
- a gate of the first PMOS transistor is coupled to the computation input node;
- a source of the first NMOS transistor is coupled to the bit-line;
- and
- a source of the first PMOS transistor is coupled to the complementary bit-line.
A circuit for in-memory computation, comprising:
- a memory cell having a bit-line and a complementary bit-line;
- a computation circuit coupled to a computation input node of the circuit and at least one of the bit-line or the complementary bit-line, wherein the computation circuit comprises a counter, a first n-type metal-oxide-semiconductor (NMOS) transistor coupled to the memory cell, and a first p-type metal-oxide-semiconductor (PMOS) transistor coupled to the memory cell, drains of the first NMOS and PMOS transistors being coupled to the counter;
- and
- an enable circuit having:
- a second NMOS transistor coupled between the computation input node and the first NMOS transistor, a gate of the second NMOS transistor being coupled to an enable input node;
- and
- a second PMOS transistor coupled between a complementary computation input node and the first PMOS transistor, a gate of the second PMOS transistor being coupled to a complementary enable input node.
A circuit for in-memory computation, comprising:
- a memory cell having a bit-line and a complementary bit-line;
- a computation circuit coupled to a computation input node of the circuit and at least one of the bit-line or the complementary bit-line, wherein the computation circuit comprises a counter, a first n-type metal-oxide-semiconductor (NMOS) transistor coupled to the memory cell, and a first p-type metal-oxide-semiconductor (PMOS) transistor coupled to the memory cell, drains of the first NMOS and PMOS transistors being coupled to the counter, and wherein a gate of the first NMOS transistor is connected with the computation input node;
- and
- an enable circuit having a second NMOS transistor coupled between the counter and the drains of the first NMOS transistor and the first PMOS transistor, a gate of the second NMOS transistor being coupled to an enable input node.
Dependencies are inferred from the claim text.