Memory array staircase structure

A method of forming a memory array, the method comprising:

• forming a multi-layer stack on a semiconductor substrate;
• etching the multi-layer stack to form a first staircase structure in a first corner region of the memory array and a second staircase structure in a second corner region of the memory array opposite the first corner region;
• depositing an inter-metal dielectric (IMD) on the multi-layer stack;
• planarizing the IMD such that a first portion of the IMD on the first staircase structure is separated from a second portion of the IMD on the second staircase structure, wherein a top surface of the second portion is level with a top surface of the first portion;
• forming a first trench in the multi-layer stack adjacent a first word line;
• depositing a memory film in the first trench and in contact with the first word line and the first portion of the IMD;
• depositing an oxide semiconductor (OS) layer on the memory film;
• and
• forming a source line and a bit line on and in contact with the OS layer.

A method comprising:

• forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising alternating layers of a first material and a second material;
• patterning the multi-layer stack to form a first staircase structure in a first corner region on the semiconductor substrate and a second staircase structure in a second corner region on the semiconductor substrate kitty corner to the first corner region;
• patterning a first trench extending through the multi-layer stack;
• depositing a memory film along sidewalls and a bottom surface of the first trench;
• and
• depositing an oxide semiconductor (OS) layer over the memory film.