US 11,776,600 B2 · Memory clock management and estimation procedures

Abstract

Methods, systems, and devices for memory clock management and estimation procedures are described. A host device may determine a quantity of clock cycles associated with a duration for accessing a memory cell of a memory array based on truncating a value of a first parameter associated with another duration for a clock to perform a clock cycle. The host device may estimate a value of a second parameter related to (e.g., inversely proportional) to the truncated value of the first parameter and related to (e.g., directly proportional) to a correction factor, and may adjust (e.g., truncate) a third parameter to determine the quantity of clock cycles. Additionally or alternatively, the host device may adjust (e.g., perform a ceiling operation on) the second parameter to determine the quantity of clock cycles. The host device may access the memory cell based on the quantity of clock cycles.

Claims25

Dependent claims

A method, comprising:

truncating a value of a first parameter associated with a first duration for a clock to perform a clock cycle;
estimating a value of a second parameter that is inversely proportional to the truncated value of the first parameter and directly proportional to a correction factor;
determining a quantity of clock cycles associated with a second duration for accessing one or more memory cells of a memory array based at least in part on adjusting a third parameter associated with the second parameter;
and
accessing the one or more memory cells of the memory array based at least in part on the determined quantity of clock cycles.

2 more elements

A non-transitory computer-readable medium comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to:

truncate a value of a first parameter associated with a first duration for a clock coupled to perform a clock cycle;
estimate a value of a second parameter that is inversely proportional to the truncated value of the first parameter and directly proportional to a correction factor;
determine a quantity of clock cycles associated with a second duration for accessing one or more memory cells of a memory array based at least in part on adjusting a third parameter associated with the second parameter;
and
access the one or more memory cells of the memory array based at least in part on the determined quantity of clock cycles.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/649,006Filed 26 Jan 2022 · us provisional application

Priority

3 Feb 2021

Published

US 2022/0246188 A14 Aug 2022

Granted

3 Oct 2023

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 7/222
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…
G11C 7/1069
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: i/O lines read…
G11C 7/1096
Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits: write circuits, e.g.…
G11C 8/18
Arrangements for selecting an address in a digital store: address timing or clocking circuits; Address control signal generation or management,…

Memory clock management and estimation procedures

Life of this patent

Memory clock management and estimation procedures

Life of this patent

Abstract

Claims25