Encoded enable clock gaters
AssigneeAdvanced Micro Devices, Inc.
InventorPatrick J. Shyvers
Life of this patent
Estimating the term…
Abstract
A processing device is provided which includes a processor and a data storage structure. The data storage structure comprises a data storage array comprising a plurality of lines. Each line comprises at least one A latch configured to store a data bit and a clock gater. The data storage structure also comprises a write data B latch configured to store, over different clock cycles, a different data bit, each to be written to the at least one A latch of one of the plurality of lines. The data storage structure also comprises a plurality of write index B latches shared by the clock gaters of the lines. The write index B latches are configured to store, over the different clock cycles, combinations of index bits having values which index one of the lines to which a corresponding data bit is to be stored.
Claims20
A processing device comprising:
- a processor;
- and
- a data storage structure comprising:
- a data storage array comprising a plurality of lines, each line comprising at least one A latch configured to store a data bit and a clock gater;
- a write data B latch configured to store, over different clock cycles, a different data bit, each to be written to the at least one A latch of one of the plurality of lines;
- and
- a plurality of write index B latches shared by the clock gaters of the plurality of lines and configured to store, over the different clock cycles, combinations of index bits having values which index one of the lines to which a corresponding data bit is to be stored.
A data storage structure for use with a processing device, the data storage structure comprising:
- a data storage array comprising a plurality of lines, each line comprising at least one first latch, configured to store a data bit, and a clock gater;
- a write data second latch configured to store, over different clock cycles, a different data bit, each to be written to the at least one first latch of one of the plurality of lines;
- and
- a plurality of write index second latches shared by the clock gaters of the plurality of lines and configured to store, over the different clock cycles, combinations of index bits, having values which index one of the lines to which a corresponding data bit is to be stored.
A method of accessing a data storage array comprising:
- providing a data bit, from a write data second latch, to each of a plurality of lines of a storage array, each line comprising at least one first latch and a clock gater;
- enabling the clock gater of one of the plurality of lines that is indexed by a combination of index bits in write index second latches shared by the clock gaters of the lines;
- updating the at least one first latch of the one line, indexed by values of the combination of index bits, with the data bit;
- and
- maintaining previously stored data in at least one first latches of the other lines not indexed by the combination of index bits.
Dependencies are inferred from the claim text.