Data processing circuit and device
AssigneeChangxin Memory Technologies, Inc.
InventorZequn Huang
Life of this patent
Estimating the term…
Abstract
An embodiment provides a data processing circuit and a device. The circuit includes: a first bank group 201 and a second bank group 202; a write circuit 203; and a read circuit 204. The write circuit 203 includes a write input cache circuit 2031, and is configured to: receive stored data from a write bus 206 through the write input cache circuit 2031, write the stored data into the first bank group 201 through a first read-write bus 207, and write the stored data into the second bank group 202 through a second read-write bus 208. The read circuit 204 includes a read output cache circuit 2041, and is configured to: read the stored data from the first bank group 201 through the first read-write bus 207, and read the stored data from the second bank group 202 through the second read-write bus 208.
Claims16
A data processing circuit, comprising:
- a first bank group and a second bank group;
- a write circuit, comprising only one write input cache circuit, the write circuit being configured to:
- receive stored data from a write bus through the write input cache circuit, write the stored data into the first bank group through a first read-write bus, and write the stored data into the second bank group through a second read-write bus;
- and
- a read circuit, comprising only one read output cache circuit, the read circuit being configured to:
- read the stored data from the first bank group through the first read-write bus, read the stored data from the second bank group through the second read-write bus, and transmit the stored data to a read bus through the read output cache circuit.
A memory, comprising two data processing circuits, each of the two data processing circuits comprising:
- a first bank group and a second bank group;
- a write circuit, comprising only one write input cache circuit, the write circuit being configured to:
- receive stored data from a write bus through the write input cache circuit, write the stored data into the first bank group through a first read-write bus, and write the stored data into the second bank group through a second read-write bus;
- and
- a read circuit, comprising only one read output cache circuit, the read circuit being configured to:
- read the stored data from the first bank group through the first read-write bus, read the stored data from the second bank group through the second read-write bus, and transmit the stored data to a read bus through the read output cache circuit;
- wherein write circuits in the two data processing circuits are connected to same write bus, and read circuits in the two data processing circuits are connected to same read bus.
An electronic device comprising a memory, wherein the memory comprises two data processing circuits, each of the two data processing circuits comprising:
- a first bank group and a second bank group;
- a write circuit, comprising only one write input cache circuit, the write circuit being configured to:
- receive stored data from a write bus through the write input cache circuit, write the stored data into the first bank group through a first read-write bus, and write the stored data into the second bank group through a second read-write bus;
- and
- a read circuit, comprising only one read output cache circuit, the read circuit being configured to:
- read the stored data from the first bank group through the first read-write bus, read the stored data from the second bank group through the second read-write bus, and transmit the stored data to a read bus through the read output cache circuit;
- wherein write circuits in the two data processing circuits are connected to same write bus, and read circuits in the two data processing circuits are connected to same read bus.
Dependencies are inferred from the claim text.