Memory device with source line control
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPerng-Fei Yuh, Yih Wang
Life of this patent
Estimating the term…
Abstract
Disclosed herein are related to a memory device including a set of memory cells and a memory controller. In one aspect, each of the set of memory cells includes a select transistor and a storage element connected in series between a corresponding bit line and a corresponding source line. In one aspect, the memory controller is configured to apply a first write voltage to a bit line coupled to a selected memory cell, apply a second write voltage to a word line coupled to a gate electrode of a select transistor of the selected memory cell during a first time period, and apply a third write voltage to a source line coupled to the selected memory cell. The second write voltage may be between the first write voltage and the third write voltage.
Claims19
A memory system:
- a set of memory cells, each of the set of memory cells including a select transistor and a storage element connected in series between a corresponding bit line and a corresponding source line;
- and
- a memory controller coupled to the set of memory cells, the memory controller to:
- apply a first write voltage to a bit line coupled to a selected memory cell of the set of memory cells during a first time period to write data to the selected memory cell,
- apply a second write voltage to a word line coupled to a gate electrode of a select transistor of the selected memory cell during the first time period, and
- apply a third write voltage to a source line coupled to the selected memory cell during the first time period, the second write voltage between the first write voltage and the third write voltage,
- wherein a first difference between the first write voltage and the second write voltage less than an allowable stress voltage of each select transistor, and a second difference between the second write voltage and the third write voltage less than the allowable stress voltage of each select transistor.
A memory system:
- a memory array including:
- a first memory cell,
- a second memory cell,
- a first word line coupled to the first memory cell and the second memory cell,
- a first source line coupled to the first memory cell, and
- a second source line coupled to the second memory cell;
- and
- a memory controller to:
- apply a first write voltage to the first word line during a first time period to write data to the first memory cell,
- apply a second write voltage to the first source line during the first time period, and
- apply the first write voltage to the second source line during the first time period.
A method comprising:
- applying, by a memory controller, a first write voltage to a bit line during a time period to write data to a selected memory cell, the bit line coupled to the selected memory cell and an unselected memory cell;
- applying, by the memory controller, a second write voltage to a word line during the time period, the word line coupled to the selected memory cell and the unselected memory cell;
- applying, by the memory controller, a third write voltage to a first source line during the time period, the first source line coupled to the selected memory cell;
- and
- applying, by the memory controller, the second write voltage to a second source line during the time period, the second source line coupled to the unselected memory cell.
Dependencies are inferred from the claim text.