Scalable in situ DRAM-based accelerators and methods of operating the same
AssigneeUniversity of Virginia Patent Foundation
InventorsKevin Skadron, Marzieh Lenjani, Abdolrasoul Sharifi, Lingxi Wu
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Abstract
Apparatus includes a plurality of memory cells (e.g., a dynamic random access memory (DRAM)) addressable as rows and columns and a plurality of matching circuits configured to be coupled to respective bit lines associated with the columns A control circuit is configured to store respective reference sequences (e.g., binary-encoded k-mer patterns) in respective ones of the columns, to sequentially provide rows of bits stored in the memory cells and bits of a query to the matching circuits, and to identify one of the reference sequences as corresponding to the query responsive to comparisons by the matching circuits.
Claims18
An apparatus comprising:
- a plurality of memory cells addressable as rows and columns;
- a plurality of matching circuits configured to be coupled to respective bit lines associated with the columns;
- and
- a control circuit configured to store respective reference sequences in respective ones of the columns, to sequentially provide rows of bits stored in the memory cells and bits of a query to the matching circuits, and to identify one of the reference sequences as corresponding to the query responsive to comparisons by the matching circuits, wherein each of the matching circuits comprises:
- an XNOR gate having a first input that receives column entries and a second input that receives bits of the query;
- an AND gate having a first input coupled to an output of the XNOR gate;
- and
- a latch having an input coupled to an output of the AND gate and an output coupled to a second input of the AND gate.
An apparatus comprising:
- a plurality of memory cells addressable as rows and columns;
- a plurality of matching circuits configured to be coupled to respective bit lines associated with the columns;
- and
- a control circuit configured to store respective reference sequences in respective ones of the columns, to sequentially provide rows of bits stored in the memory cells and bits of a query to the matching circuits, and to identify one of the reference sequences as corresponding to the query responsive to comparisons by the matching circuits,
- wherein the control circuit is configured to terminate provision of rows to the matching circuits responsive to the matching circuits indicating that all of the references sequences lack at least one bit of the query,
- wherein the control circuit comprises respective segment evaluation circuits coupled to respective groups of the matching circuits and configured to generate respective match indicators for respective subgroups of each row of bits provided to the matching circuits and wherein the control circuit is configured to terminate provision of rows to the matching circuit responsive to the segment evaluation circuits, and
- wherein each of the segment evaluation circuits comprises:
- a plurality of cascaded OR gates that receive inputs from respective ones of the matching circuits;
- and
- a segment register that receives and stores a value output from the plurality of cascaded OR gates and provides the stored output to another one of the segment evaluation circuits.
A method comprising:
- storing respective reference sequences in respective ones of columns of a plurality of memory cells addressable as rows and columns;
- sequentially providing rows of bits stored in the memory cells and bits of a query to a plurality of matching circuits coupled to respective bit lines associated with the columns;
- and
- identifying one of the reference sequences as corresponding to the query responsive to comparisons by the matching circuits,
- wherein each of the matching circuits comprises:
- an XNOR gate having a first input that receives column entries and a second input that receives bits of the query;
- an AND gate having a first input coupled to an output of the XNOR gate;
- and
- a latch having an input coupled to an output of the AND gate and an output coupled to a second input of the AND gate.
Dependencies are inferred from the claim text.