Semiconductor device and continuous reading method
AssigneeWinbond Electronics Corp.
InventorSho Okabe
Life of this patent
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Abstract
The invention provides a semiconductor device and a continuous reading method for suppressing fluctuations of a precharging voltage caused by an increase in a precharging time. The continuous reading method of a NAND flash memory of the invention includes the following steps: a first voltage (VCLMP1+Vth) is applied to a gate of a transistor (BLCLAMP) connected to a bit line and a voltage is supplied to the bit line via the transistor (BLCLAMP) to start precharging of the bit line; and a second voltage (VCLMP1+Vth−α) lower than the first voltage is applied to the gate of the transistor (BLCLAMP) when the precharging time caused by the application of the first voltage has elapsed for a certain period of time.
Claims14
A continuous reading method for NAND flash memory, comprising:
- applying a first voltage to a gate of a transistor connected to a bit line, and supplying a voltage to the bit line via the transistor to start precharging of the bit line;
- and
- applying a second voltage lower than the first voltage to the gate of the transistor when a precharging time caused by the application of the first voltage has elapsed for a certain period of time, wherein the step of applying the second voltage comprises applying the second voltage until a latch circuit is able to be initialized when the latch circuit receiving a charge of a reading node is unable to be initialized, wherein the certain period of time is determined based on time required to determine whether the latch circuit is able to be initialized.
A semiconductor device, comprising:
- a NAND memory cell array;
- a reading unit, reading data from a selected page of the memory cell array;
- and
- an output unit, outputting the data read out by the reading unit to the outside,
- wherein the reading unit comprises a page buffer/reading circuit connected to the memory cell array via a bit line,
- the page buffer/reading circuit comprises a transistor for supplying a precharging voltage to the bit line, and
- when precharging the bit line, the page buffer/reading circuit applies a first voltage to a gate of the transistor to start to precharge, and applies a second voltage less than the first voltage to the gate of the transistor when a precharging time has elapsed for a certain period of time, wherein the page buffer/reading circuit applies the second voltage when a latch circuit receiving a charge of a reading node is unable to be initialized, the applying the second voltage continues until the latch circuit is able to be initialized, and the certain period of time is determined based on time required to determine whether the latch circuit is able to be initialized.
Dependencies are inferred from the claim text.